From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: "Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH] target/ppc: Add extra float instructions to POWER5P processors
Date: Mon, 10 Jan 2022 17:19:59 +0100 [thread overview]
Message-ID: <20220110161959.758997-1-clg@kaod.org> (raw)
ISA v2.03 introduced Floating Round to Integer instructions : frin,
friz, frip, and frim. Add them to POWER5+.
The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
Estimate) instruction which was introduced in ISA v2.0x. The
architecture document says its optional and that might the reason why
it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
use it under QEMU.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index f15a52259c90..e30e86fe9d04 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6953,6 +6953,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
--
2.31.1
next reply other threads:[~2022-01-10 16:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 16:19 Cédric Le Goater [this message]
2022-01-10 18:42 ` [PATCH] target/ppc: Add extra float instructions to POWER5P processors BALATON Zoltan
2022-01-10 19:28 ` Cédric Le Goater
2022-01-12 11:38 ` Cédric Le Goater
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