[PATCH] target/ppc: Add extra float instructions to POWER5P processors

[PATCH] target/ppc: Add extra float instructions to POWER5P processors

[Cédric Le Goater]

ISA v2.03 introduced Floating Round to Integer instructions : frin,
friz, frip, and frim. Add them to POWER5+.

The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
Estimate) instruction which was introduced in ISA v2.0x. The
architecture document says its optional and that might the reason why
it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
use it under QEMU.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/cpu_init.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index f15a52259c90..e30e86fe9d04 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6953,6 +6953,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
                        PPC_FLOAT_STFIWX |
+                       PPC_FLOAT_EXT |
                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
-- 
2.31.1

Re: [PATCH] target/ppc: Add extra float instructions to POWER5P processors

[BALATON Zoltan]

[-- Attachment #1: Type: text/plain, Size: 1510 bytes --]

On Mon, 10 Jan 2022, Cédric Le Goater wrote:
> ISA v2.03 introduced Floating Round to Integer instructions : frin,
> friz, frip, and frim. Add them to POWER5+.
>
> The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
> Estimate) instruction which was introduced in ISA v2.0x. The
> architecture document says its optional and that might the reason why

There's a grammar error in this sentence. I think it should be "might be 
the reason" or "might have been the reason", not sure which is more 
correct but "be" is missing here for sure. Another one: it should be 
"it's" instead of "its" in this context.

Regards,
BALATON Zoltan

> it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
> use it under QEMU.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/cpu_init.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index f15a52259c90..e30e86fe9d04 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -6953,6 +6953,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
>                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
>                        PPC_FLOAT_STFIWX |
> +                       PPC_FLOAT_EXT |
>                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
>                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
>                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
>

Re: [PATCH] target/ppc: Add extra float instructions to POWER5P processors

[Cédric Le Goater]

On 1/10/22 19:42, BALATON Zoltan wrote:
> On Mon, 10 Jan 2022, Cédric Le Goater wrote:
>> ISA v2.03 introduced Floating Round to Integer instructions : frin,
>> friz, frip, and frim. Add them to POWER5+.
>>
>> The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
>> Estimate) instruction which was introduced in ISA v2.0x. The
>> architecture document says its optional and that might the reason why
> 
> There's a grammar error in this sentence. I think it should be "might be the reason" or "might have been the reason", not sure which is more correct but "be" is missing here for sure. Another one: it should be "it's" instead of "its" in this context.

A "be" is missing indeed ! Fixed.

Thanks,

C.

> 
> Regards,
> BALATON Zoltan
> 
>> it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
>> use it under QEMU.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> target/ppc/cpu_init.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>> index f15a52259c90..e30e86fe9d04 100644
>> --- a/target/ppc/cpu_init.c
>> +++ b/target/ppc/cpu_init.c
>> @@ -6953,6 +6953,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
>>                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
>>                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
>>                        PPC_FLOAT_STFIWX |
>> +                       PPC_FLOAT_EXT |
>>                        PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
>>                        PPC_MEM_SYNC | PPC_MEM_EIEIO |
>>                        PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
>>

Re: [PATCH] target/ppc: Add extra float instructions to POWER5P processors

[Cédric Le Goater]

On 1/10/22 17:19, Cédric Le Goater wrote:
> ISA v2.03 introduced Floating Round to Integer instructions : frin,
> friz, frip, and frim. Add them to POWER5+.
> 
> The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
> Estimate) instruction which was introduced in ISA v2.0x. The
> architecture document says its optional and that might the reason why
> it has been kept under the PPC_FLOAT_EXT. This means 970 CPUs can not
> use it under QEMU.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>


Applied to ppc7.0.

Thanks,

C.