From: Idan Horowitz <idan.horowitz@gmail.com>
To: qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
Idan Horowitz <idan.horowitz@gmail.com>,
qemu-devel@nongnu.org, pbonzini@redhat.com
Subject: [PATCH 2/2] target/arm: Bail out early on 0-length tlb range invalidate
Date: Mon, 10 Jan 2022 18:47:54 +0200 [thread overview]
Message-ID: <20220110164754.1066025-2-idan.horowitz@gmail.com> (raw)
In-Reply-To: <20220110164754.1066025-1-idan.horowitz@gmail.com>
If the given range specifies no addresses to be flushed there's no reason
to schedule a function on all CPUs that does nothing.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
---
target/arm/helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cfca0f5ba6..1e819835c2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4564,6 +4564,10 @@ static void do_rvae_write(CPUARMState *env, uint64_t value,
length = tlbi_aa64_range_get_length(env, value);
bits = tlbbits_for_regime(env, one_idx, baseaddr);
+ if (length == 0) {
+ return;
+ }
+
if (synced) {
tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
baseaddr,
--
2.33.1
next prev parent reply other threads:[~2022-01-10 16:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-10 16:47 [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range flush Idan Horowitz
2022-01-10 16:47 ` Idan Horowitz [this message]
2022-01-25 22:05 ` [PATCH 2/2] target/arm: Bail out early on 0-length tlb range invalidate Richard Henderson
2022-01-25 22:06 ` Peter Maydell
2022-01-25 23:34 ` Richard Henderson
2022-01-14 15:48 ` [PATCH 1/2] accel/tcg: Optimize jump cache flush during tlb range flush Alex Bennée
2022-01-14 16:41 ` Idan Horowitz
2022-01-14 20:56 ` Idan Horowitz
2022-01-25 21:55 ` Richard Henderson
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