From: Yang Zhong <yang.zhong@intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: yang.zhong@intel.com, "Christopherson, ,
Sean" <seanjc@google.com>,
"jing2.liu@linux.intel.com" <jing2.liu@linux.intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Wang, Wei W" <wei.w.wang@intel.com>,
"Zeng, Guang" <guang.zeng@intel.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>
Subject: Re: [RFC PATCH 4/7] x86: Add XFD faulting bit for state components
Date: Tue, 11 Jan 2022 13:32:32 +0800 [thread overview]
Message-ID: <20220111053232.GA10991@yangzhon-Virtual> (raw)
In-Reply-To: <BN9PR11MB527604A587F7F84B9DF5F1238C509@BN9PR11MB5276.namprd11.prod.outlook.com>
On Mon, Jan 10, 2022 at 04:38:18PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang <yang.zhong@intel.com>
> > Sent: Friday, January 7, 2022 5:32 PM
> >
> > From: Jing Liu <jing2.liu@intel.com>
> >
> > Intel introduces XFD faulting mechanism for extended
> > XSAVE features to dynamically enable the features in
> > runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
> > as 1, it indicates support for XFD faulting of this
> > state component.
> >
> > Signed-off-by: Jing Liu <jing2.liu@intel.com>
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > ---
> > target/i386/cpu.h | 2 +-
> > target/i386/cpu.c | 2 +-
> > target/i386/kvm/kvm-cpu.c | 1 +
> > 3 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> > index 79023fe723..22f7ff40a6 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -1375,7 +1375,7 @@
> > QEMU_BUILD_BUG_ON(sizeof(XSaveXTILE_DATA) != 0x2000);
> > typedef struct ExtSaveArea {
> > uint32_t feature, bits;
> > uint32_t offset, size;
> > - uint32_t need_align;
> > + uint32_t need_align, support_xfd;
>
> why each flag be a 32-bit field?
>
Using the uint32_t to define those flags for below ecx value
*ecx = (esa->need_align << 1) | (esa->support_xfd << 2);
> also it's more natural to have them in separate lines, though I'm not
> sure why existing fields are put this way (possibly due to short names?).
>
Yes, support_xfd flag will be in another line to define, thanks!
Yang
> > } ExtSaveArea;
> >
> > #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index dd2c919c33..1adc3f0f99 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -5495,7 +5495,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t
> > index, uint32_t count,
> > const ExtSaveArea *esa = &x86_ext_save_areas[count];
> > *eax = esa->size;
> > *ebx = esa->offset;
> > - *ecx = esa->need_align << 1;
> > + *ecx = (esa->need_align << 1) | (esa->support_xfd << 2);
> > }
> > }
> > break;
> > diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
> > index 6c4c1c6f9d..3b3c203f11 100644
> > --- a/target/i386/kvm/kvm-cpu.c
> > +++ b/target/i386/kvm/kvm-cpu.c
> > @@ -108,6 +108,7 @@ static void kvm_cpu_xsave_init(void)
> >
> > uint32_t ecx = kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX);
> > esa->need_align = ecx & (1u << 1) ? 1 : 0;
> > + esa->support_xfd = ecx & (1u << 2) ? 1 : 0;
> > }
> > }
> > }
next prev parent reply other threads:[~2022-01-11 5:52 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-07 9:31 [RFC PATCH 0/7] AMX support in Qemu Yang Zhong
2022-01-07 9:31 ` [RFC PATCH 1/7] x86: Fix the 64-byte boundary enumeration for extended state Yang Zhong
2022-01-10 8:20 ` Tian, Kevin
2022-01-11 2:22 ` Yang Zhong
2022-01-18 12:37 ` Paolo Bonzini
2022-01-21 7:14 ` Yang Zhong
2022-01-07 9:31 ` [RFC PATCH 2/7] x86: Add AMX XTILECFG and XTILEDATA components Yang Zhong
2022-01-10 8:23 ` Tian, Kevin
2022-01-11 2:32 ` Yang Zhong
2022-01-18 12:39 ` Paolo Bonzini
2022-01-21 7:15 ` Yang Zhong
2022-01-07 9:31 ` [RFC PATCH 3/7] x86: Grant AMX permission for guest Yang Zhong
2022-01-10 8:36 ` Tian, Kevin
2022-01-11 6:46 ` Yang Zhong
2022-01-18 12:52 ` Paolo Bonzini
2022-01-18 13:06 ` Paolo Bonzini
2022-01-21 7:21 ` Yang Zhong
2022-01-07 9:31 ` [RFC PATCH 4/7] x86: Add XFD faulting bit for state components Yang Zhong
2022-01-10 8:38 ` Tian, Kevin
2022-01-11 5:32 ` Yang Zhong [this message]
2022-01-18 12:52 ` Paolo Bonzini
2022-01-21 7:18 ` Yang Zhong
2022-01-07 9:31 ` [RFC PATCH 5/7] x86: Add AMX CPUIDs enumeration Yang Zhong
2022-01-07 9:31 ` [RFC PATCH 6/7] x86: Use new XSAVE ioctls handling Yang Zhong
2022-01-10 8:40 ` Tian, Kevin
2022-01-10 9:47 ` Zeng Guang
2022-01-11 2:30 ` Tian, Kevin
2022-01-11 4:29 ` Zeng Guang
2022-01-12 2:51 ` Zeng Guang
2022-01-12 4:34 ` Wang, Wei W
2022-01-07 9:31 ` [RFC PATCH 7/7] x86: Support XFD and AMX xsave data migration Yang Zhong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220111053232.GA10991@yangzhon-Virtual \
--to=yang.zhong@intel.com \
--cc=guang.zeng@intel.com \
--cc=jing2.liu@linux.intel.com \
--cc=kevin.tian@intel.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=seanjc@google.com \
--cc=wei.w.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).