From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Hervé Poussineau" <hpoussin@reactos.org>,
"Bernhard Beschow" <shentey@gmail.com>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 3/3] isa/piix4: Resolve global variables
Date: Wed, 12 Jan 2022 22:36:28 +0100 [thread overview]
Message-ID: <20220112213629.9126-4-shentey@gmail.com> (raw)
In-Reply-To: <20220112213629.9126-1-shentey@gmail.com>
Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant and pci_irq_levels can be moved into PIIX4State.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/isa/piix4.c | 22 +++++++++-------------
include/hw/southbridge/piix.h | 2 --
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index a31e9714cf..964e09cf7f 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -39,14 +39,14 @@
#include "sysemu/runstate.h"
#include "qom/object.h"
-PCIDevice *piix4_dev;
-
struct PIIX4State {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa;
qemu_irq i8259[ISA_NUM_IRQS];
+ int pci_irq_levels[PIIX_NUM_PIRQS];
+
RTCState rtc;
/* Reset Control Register */
MemoryRegion rcr_mem;
@@ -55,24 +55,22 @@ struct PIIX4State {
OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
-static int pci_irq_levels[4];
-
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
PIIX4State *s = opaque;
- pci_irq_levels[irq_num] = level;
+ s->pci_irq_levels[irq_num] = level;
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
- if (pic_irq < 16) {
+ pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
+ if (pic_irq < ISA_NUM_IRQS) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
- for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
- pic_level |= pci_irq_levels[i];
+ for (i = 0; i < PIIX_NUM_PIRQS; i++) {
+ if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
+ pic_level |= s->pci_irq_levels[i];
}
}
qemu_set_irq(s->i8259[pic_irq], pic_level);
@@ -223,8 +221,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
-
- piix4_dev = dev;
}
static void piix4_init(Object *obj)
@@ -323,7 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
NULL, 0, NULL);
}
- pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4);
+ pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
for (int i = 0; i < ISA_NUM_IRQS; i++) {
s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 6387f2b612..f63f83e5c6 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State;
DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
TYPE_PIIX3_PCI_DEVICE)
-extern PCIDevice *piix4_dev;
-
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
--
2.34.1
next prev parent reply other threads:[~2022-01-12 22:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-12 21:36 [PATCH 0/3] malta: Move PCI interrupt handling from gt64xxx to piix4 Bernhard Beschow
2022-01-12 21:36 ` [PATCH 1/3] " Bernhard Beschow
2022-01-30 22:34 ` Philippe Mathieu-Daudé via
2022-01-12 21:36 ` [PATCH 2/3] pci: Always pass own DeviceState to pci_map_irq_fn's Bernhard Beschow
2022-01-14 13:29 ` Peter Maydell
2022-01-30 22:36 ` Philippe Mathieu-Daudé via
2022-01-12 21:36 ` Bernhard Beschow [this message]
2022-01-14 13:36 ` [PATCH 3/3] isa/piix4: Resolve global variables Peter Maydell
2022-01-30 22:53 ` Philippe Mathieu-Daudé via
2022-02-09 23:16 ` BB
2022-02-10 7:18 ` Michael S. Tsirkin
2022-01-30 22:39 ` Philippe Mathieu-Daudé via
2022-01-13 9:24 ` [PATCH 0/3] malta: Move PCI interrupt handling from gt64xxx to piix4 Philippe Mathieu-Daudé
2022-01-13 11:22 ` Bernhard Beschow
2022-01-13 11:53 ` Philippe Mathieu-Daudé
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