From: Weiwei Li <liweiwei@iscas.ac.cn>
To: anup@brainfault.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com
Subject: [PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
Date: Tue, 18 Jan 2022 09:17:08 +0800 [thread overview]
Message-ID: <20220118011711.7243-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220118011711.7243-1-liweiwei@iscas.ac.cn>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 26608ddf1c..1820188f41 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -626,6 +626,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
next prev parent reply other threads:[~2022-01-18 1:20 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-18 1:17 [PATCH v5 0/5] support subsets of virtual memory extension Weiwei Li
2022-01-18 1:17 ` [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li
2022-01-18 3:30 ` Anup Patel
2022-01-18 4:51 ` Alistair Francis
2022-01-18 11:54 ` Guo Ren
2022-01-20 13:47 ` Guo Ren
2022-01-20 22:28 ` LIU Zhiwei
2022-01-21 1:50 ` Guo Ren
2022-01-21 2:08 ` LIU Zhiwei
2022-01-18 8:33 ` Guo Ren
2022-01-18 8:51 ` Anup Patel
2022-01-18 11:15 ` Guo Ren
2022-01-18 11:25 ` Anup Patel
2022-01-18 11:28 ` Anup Patel
2022-01-18 11:57 ` Guo Ren
2022-01-18 11:29 ` Weiwei Li
2022-01-19 3:14 ` LIU Zhiwei
2022-01-18 1:17 ` Weiwei Li [this message]
2022-01-18 1:17 ` [PATCH v5 3/5] target/riscv: add support for svnapot extension Weiwei Li
2022-01-18 3:32 ` Anup Patel
2022-01-18 8:32 ` Weiwei Li
2022-01-18 1:17 ` [PATCH v5 4/5] target/riscv: add support for svinval extension Weiwei Li
2022-01-18 1:17 ` [PATCH v5 5/5] target/riscv: add support for svpbmt extension Weiwei Li
2022-01-18 3:35 ` Anup Patel
2022-01-18 8:33 ` Weiwei Li
2022-01-18 9:09 ` Weiwei Li
2022-01-18 11:04 ` Anup Patel
2022-01-18 11:21 ` Weiwei Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220118011711.7243-3-liweiwei@iscas.ac.cn \
--to=liweiwei@iscas.ac.cn \
--cc=alistair.francis@wdc.com \
--cc=anup@brainfault.org \
--cc=bin.meng@windriver.com \
--cc=lazyparser@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=wangjunqiang@iscas.ac.cn \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).