From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
Date: Tue, 18 Jan 2022 09:45:07 +0800 [thread overview]
Message-ID: <20220118014522.13613-5-frank.chang@sifive.com> (raw)
In-Reply-To: <20220118014522.13613-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support all vector integer instructions,
except that the vmulh integer multiply variants that return the
high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx,
vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++----
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 0bf41aaa1e..e64dddda28 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1908,14 +1908,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
GEN_OPIVX_TRANS(vmax_vx, opivx_check)
/* Vector Single-Width Integer Multiply Instructions */
+
+static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
+{
+ /*
+ * All Zve* extensions support all vector integer instructions,
+ * except that the vmulh integer multiply variants
+ * that return the high word of the product
+ * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+ * are not included for EEW=64 in Zve64*. (Section 18.2)
+ */
+ return opivv_check(s, a) &&
+ (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
+static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
+{
+ /*
+ * All Zve* extensions support all vector integer instructions,
+ * except that the vmulh integer multiply variants
+ * that return the high word of the product
+ * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx)
+ * are not included for EEW=64 in Zve64*. (Section 18.2)
+ */
+ return opivx_check(s, a) &&
+ (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true);
+}
+
GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
-GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
-GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check)
GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
-GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
-GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check)
/* Vector Integer Divide Instructions */
GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
--
2.31.1
next prev parent reply other threads:[~2022-01-18 1:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-18 1:45 [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
2022-01-18 1:45 ` [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
2022-01-18 1:45 ` [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns frank.chang
2022-01-18 1:45 ` [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
2022-01-18 4:42 ` Alistair Francis
2022-01-18 1:45 ` frank.chang [this message]
2022-01-18 1:45 ` [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns frank.chang
2022-01-18 1:45 ` [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns frank.chang
2022-01-18 1:45 ` [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns frank.chang
2022-01-18 1:45 ` [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns frank.chang
2022-01-18 1:45 ` [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing " frank.chang
2022-01-18 1:45 ` [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on frank.chang
2022-01-18 1:45 ` [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V frank.chang
2022-01-18 1:45 ` [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns frank.chang
2022-01-18 1:45 ` [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns frank.chang
2022-01-18 1:45 ` [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns frank.chang
2022-01-18 1:45 ` [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns frank.chang
2022-01-18 1:45 ` [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing " frank.chang
2022-01-18 1:45 ` [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on frank.chang
2022-01-18 22:25 ` [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Alistair Francis
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