From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB6F3C433EF for ; Wed, 19 Jan 2022 15:38:49 +0000 (UTC) Received: from localhost ([::1]:37570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nAD2u-0003DF-Cv for qemu-devel@archiver.kernel.org; Wed, 19 Jan 2022 10:38:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:40838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nACs2-0007UD-NH for qemu-devel@nongnu.org; Wed, 19 Jan 2022 10:27:35 -0500 Received: from [2607:f8b0:4864:20::429] (port=43683 helo=mail-pf1-x429.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nACs1-0000UD-2t for qemu-devel@nongnu.org; Wed, 19 Jan 2022 10:27:34 -0500 Received: by mail-pf1-x429.google.com with SMTP id 78so2601795pfu.10 for ; Wed, 19 Jan 2022 07:27:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lRApxAcJ4/diR+34YkzkUBVmXWfRZ1nhANhRHSzXZgk=; b=iE8Qdpki1LIJ9ixn65EHmBOp6iK8ZISAIlfCBUIwwhuuQjhy30o895wfY4poGetogh /w5sxQhgsK0/IDoyAnA3JuGI1dmBAhd2Sl7QXHx1RkRzdMSzHtBVoSjQeE07U+95XCLu uwMcHabA99m10bhoRHIdQiWggmj/OW+0UBzmiPENdZ+nbyySd2usJ7lT/+7Ppr9Z9UZk sdg50wrJxYNmwpChQebtTuqu2cRmf3pvCLtOCnJmIKgvcaGQ9SEU4xEkCvVADwDuGSCn 336aFMnmjoJs6zPKj34TCzDqwyxukwh8Xmll6zMuqbrnLsXtlfGvnP+TmTBsy5btRf0B Llgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lRApxAcJ4/diR+34YkzkUBVmXWfRZ1nhANhRHSzXZgk=; b=tucUtMZH2rhqdC34mCopbtJ87hhBY2IN7xEPcn3dx/9ZjHaHRPgeZe2hYRPKV1N2h/ nQM4NBuWOKTv37RnrtK/5mYbONFycyEg0kLQ77fjn6ff3VGy6gxOQsGcj9vgJg28U080 ZpztsvqbgeQI8HrfH1t9+5tqE2Y/h+bovnExhyR0QKbMHfYY1xczNPP9to6gG6V6aTv3 H4diRFeSBBMo2Qoghm00NI50G9eZpH9kJCpnOB7HRKJT1In6WJLPFPhSe4cAnQPCj07A 0G8XFnGeORAl3qqUxP2VEjP8fqiO7Mg8G+ofgpxIncZGMlh7+zPHZMHUdlRTqzbWG0QL pkVA== X-Gm-Message-State: AOAM533U3B4qLj5CHkVzNFUj+SpvF4+ymcmvktoGMcKSIH61uKLj8yv7 JSZC/ZDVFhRLajD9SU3c2wJknQ== X-Google-Smtp-Source: ABdhPJxVnCFgBgxIBN42xKlShFg6uVuwNw9LAmfJEMec13FqX+Nv2JTCR8nO4UlgHfyVQ/yvPUaJpw== X-Received: by 2002:a63:2c07:: with SMTP id s7mr27424957pgs.191.1642606042029; Wed, 19 Jan 2022 07:27:22 -0800 (PST) Received: from localhost.localdomain ([122.179.40.245]) by smtp.gmail.com with ESMTPSA id 187sm26791pfv.157.2022.01.19.07.27.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jan 2022 07:27:20 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs Date: Wed, 19 Jan 2022 20:56:03 +0530 Message-Id: <20220119152614.27548-13-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220119152614.27548-1-anup@brainfault.org> References: <20220119152614.27548-1-anup@brainfault.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::429 (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::429; envelope-from=anup@brainfault.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interrupts above 12 so we add dummy implementation (i.e. read zero and ignore write) of AIA interrupt filtering CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/csr.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3128adceae..37a66942cb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -158,6 +158,15 @@ static RISCVException any32(CPURISCVState *env, int csrno) } +static int aia_any(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + static int aia_any32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -557,6 +566,12 @@ static RISCVException read_zero(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException write_ignore(CPURISCVState *env, int csrno, + target_ulong val) +{ + return RISCV_EXCP_NONE; +} + static RISCVException read_mhartid(CPURISCVState *env, int csrno, target_ulong *val) { @@ -2528,9 +2543,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval }, [CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip }, + /* Virtual Interrupts for Supervisor Level (AIA) */ + [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore }, + [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore }, + /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, [CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh }, + [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore }, + [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, /* Supervisor Trap Setup */ @@ -2584,12 +2605,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst }, /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ + [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore }, [CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl }, [CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 }, [CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 }, /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh }, + [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore }, [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph }, [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h }, [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h }, -- 2.25.1