From: Anup Patel <anup@brainfault.org>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
Anup Patel <anup@brainfault.org>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Atish Patra <atishp@atishpatra.org>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
Date: Wed, 19 Jan 2022 20:56:14 +0530 [thread overview]
Message-ID: <20220119152614.27548-24-anup@brainfault.org> (raw)
In-Reply-To: <20220119152614.27548-1-anup@brainfault.org>
From: Anup Patel <anup.patel@wdc.com>
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/virt.c | 10 ++++++++++
include/hw/riscv/virt.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index dc1b3dc751..367d01d3a9 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -45,6 +45,16 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
#if VIRT_IMSIC_GROUP_MAX_SIZE < \
IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7898c574af..78f450eb60 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX_BITS 3
+#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
#define VIRT_SOCKETS_MAX_BITS 2
#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
--
2.25.1
next prev parent reply other threads:[~2022-01-19 16:48 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 15:25 [PATCH v8 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-19 15:25 ` [PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2022-01-19 15:25 ` [PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel
2022-01-19 15:25 ` [PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2022-01-19 15:25 ` [PATCH v8 06/23] target/riscv: Add AIA cpu feature Anup Patel
2022-01-19 15:25 ` [PATCH v8 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2022-01-19 15:26 ` [PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2022-01-20 7:52 ` Frank Chang
2022-01-19 15:26 ` [PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2022-01-19 15:26 ` [PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2022-01-20 23:55 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2022-01-20 23:59 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2022-01-19 15:26 ` [PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2022-01-19 15:26 ` [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2022-01-19 15:37 ` Frank Chang
2022-01-19 16:20 ` Anup Patel
2022-01-20 8:19 ` Frank Chang
2022-01-20 12:05 ` Anup Patel
2022-01-20 13:25 ` Frank Chang
2022-01-19 15:26 ` [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2022-01-24 21:35 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2022-01-28 1:54 ` Alistair Francis
2022-01-28 3:50 ` Anup Patel
2022-01-19 15:26 ` [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2022-01-28 1:50 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 22/23] docs/system: riscv: Document AIA options for " Anup Patel
2022-01-19 15:26 ` Anup Patel [this message]
2022-01-20 12:11 ` [PATCH v8 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-21 6:16 ` Alistair Francis
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