From: Anup Patel <anup@brainfault.org>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
Anup Patel <anup@brainfault.org>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Atish Patra <atishp@atishpatra.org>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts
Date: Wed, 19 Jan 2022 20:55:55 +0530 [thread overview]
Message-ID: <20220119152614.27548-5-anup@brainfault.org> (raw)
In-Reply-To: <20220119152614.27548-1-anup@brainfault.org>
From: Anup Patel <anup.patel@wdc.com>
The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu_helper.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d3ff1e1c78..7e60e092c8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -328,6 +328,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
}
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+ if (enable) {
+ /*
+ * The guest external interrupts from an interrupt controller are
+ * delivered only when the Guest/VM is running (i.e. V=1). This means
+ * any guest external interrupt which is triggered while the Guest/VM
+ * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+ * with sluggish response to serial console input and other I/O events.
+ *
+ * To solve this, we check and inject interrupt after setting V=1.
+ */
+ riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+ }
}
bool riscv_cpu_two_stage_lookup(int mmu_idx)
--
2.25.1
next prev parent reply other threads:[~2022-01-19 16:06 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-19 15:25 [PATCH v8 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-19 15:25 ` [PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2022-01-19 15:25 ` [PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2022-01-19 15:25 ` Anup Patel [this message]
2022-01-19 15:25 ` [PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2022-01-19 15:25 ` [PATCH v8 06/23] target/riscv: Add AIA cpu feature Anup Patel
2022-01-19 15:25 ` [PATCH v8 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2022-01-19 15:25 ` [PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2022-01-19 15:26 ` [PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2022-01-20 7:52 ` Frank Chang
2022-01-19 15:26 ` [PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2022-01-19 15:26 ` [PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2022-01-20 23:55 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2022-01-20 23:59 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2022-01-19 15:26 ` [PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2022-01-19 15:26 ` [PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2022-01-19 15:26 ` [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2022-01-19 15:37 ` Frank Chang
2022-01-19 16:20 ` Anup Patel
2022-01-20 8:19 ` Frank Chang
2022-01-20 12:05 ` Anup Patel
2022-01-20 13:25 ` Frank Chang
2022-01-19 15:26 ` [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2022-01-24 21:35 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2022-01-28 1:54 ` Alistair Francis
2022-01-28 3:50 ` Anup Patel
2022-01-19 15:26 ` [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2022-01-28 1:50 ` Alistair Francis
2022-01-19 15:26 ` [PATCH v8 22/23] docs/system: riscv: Document AIA options for " Anup Patel
2022-01-19 15:26 ` [PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Anup Patel
2022-01-20 12:11 ` [PATCH v8 00/23] QEMU RISC-V AIA support Anup Patel
2022-01-21 6:16 ` Alistair Francis
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