From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
richard.henderson@linaro.org, palmer@dabbelt.com,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN
Date: Thu, 20 Jan 2022 20:20:37 +0800 [thread overview]
Message-ID: <20220120122050.41546-11-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com>
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 12 ++++++++----
target/riscv/op_helper.c | 3 ++-
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 04d3ea237f..631bc1f09e 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -924,7 +924,8 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
{
- if (get_xl(ctx) < MXL_RV128) {
+ RISCVMXL xl = get_xl(ctx);
+ if (xl < MXL_RV128) {
TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
/*
@@ -935,7 +936,8 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
+ (target_ulong)-1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
} else {
TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -1013,7 +1015,8 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
{
- if (get_xl(ctx) < MXL_RV128) {
+ RISCVMXL xl = get_xl(ctx);
+ if (xl < MXL_RV128) {
TCGv src = tcg_constant_tl(a->rs1);
/*
@@ -1024,7 +1027,8 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX :
+ (target_ulong)-1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
} else {
TCGv src = tcg_constant_tl(a->rs1);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 67693cb42b..1a75ba11e6 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
{
- RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+ target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1;
+ RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
if (ret != RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC());
--
2.25.1
next prev parent reply other threads:[~2022-01-20 16:29 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-20 12:20 [PATCH v8 00/23] Support UXL filed in xstatus LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 02/23] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 05/23] target/riscv: Create xl field in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 09/23] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-20 12:20 ` LIU Zhiwei [this message]
2022-01-20 12:20 ` [PATCH v8 11/23] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 15/23] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 18/23] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 19/23] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor LIU Zhiwei
2022-01-20 21:25 ` Alistair Francis
2022-01-20 12:20 ` [PATCH v8 22/23] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-21 0:03 ` [PATCH v8 00/23] Support UXL filed in xstatus Alistair Francis
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