From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
richard.henderson@linaro.org, palmer@dabbelt.com,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base]
Date: Thu, 20 Jan 2022 20:20:39 +0800 [thread overview]
Message-ID: <20220120122050.41546-13-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com>
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 32 ++++++++------------------------
1 file changed, 8 insertions(+), 24 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2a88bd99dc..43e2ec6dce 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -38,8 +38,8 @@ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
/* globals for PM CSRs */
-static TCGv pm_mask[4];
-static TCGv pm_base[4];
+static TCGv pm_mask;
+static TCGv pm_base;
#include "exec/gen-icount.h"
@@ -109,8 +109,6 @@ typedef struct DisasContext {
TCGv temp[4];
/* PointerMasking extension */
bool pm_enabled;
- TCGv pm_mask;
- TCGv pm_base;
} DisasContext;
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -403,8 +401,8 @@ static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
return src;
} else {
temp = temp_new(s);
- tcg_gen_andc_tl(temp, src, s->pm_mask);
- tcg_gen_or_tl(temp, temp, s->pm_base);
+ tcg_gen_andc_tl(temp, src, pm_mask);
+ tcg_gen_or_tl(temp, temp, pm_base);
return temp;
}
}
@@ -929,10 +927,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
- int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
- ctx->pm_mask = pm_mask[priv];
- ctx->pm_base = pm_base[priv];
-
ctx->zero = tcg_constant_tl(0);
}
@@ -1050,19 +1044,9 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
"load_val");
-#ifndef CONFIG_USER_ONLY
/* Assign PM CSRs to tcg globals */
- pm_mask[PRV_U] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
- pm_base[PRV_U] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
- pm_mask[PRV_S] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
- pm_base[PRV_S] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
- pm_mask[PRV_M] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
- pm_base[PRV_M] =
- tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
-#endif
+ pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
+ "pmmask");
+ pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
+ "pmbase");
}
--
2.25.1
next prev parent reply other threads:[~2022-01-20 16:51 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-20 12:20 [PATCH v8 00/23] Support UXL filed in xstatus LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 02/23] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 05/23] target/riscv: Create xl field in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 09/23] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 11/23] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-20 12:20 ` LIU Zhiwei [this message]
2022-01-20 12:20 ` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 15/23] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 18/23] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 19/23] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor LIU Zhiwei
2022-01-20 21:25 ` Alistair Francis
2022-01-20 12:20 ` [PATCH v8 22/23] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-21 0:03 ` [PATCH v8 00/23] Support UXL filed in xstatus Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220120122050.41546-13-zhiwei_liu@c-sky.com \
--to=zhiwei_liu@c-sky.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=guoren@linux.alibaba.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).