From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
richard.henderson@linaro.org, palmer@dabbelt.com,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v8 15/23] target/riscv: Split out the vill from vtype
Date: Thu, 20 Jan 2022 20:20:42 +0800 [thread overview]
Message-ID: <20220120122050.41546-16-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com>
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 3 +--
target/riscv/csr.c | 13 ++++++++++++-
target/riscv/machine.c | 5 +++--
target/riscv/vector_helper.c | 3 ++-
5 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 89621e1996..6c740b92c1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -125,6 +125,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ bool vill;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 502aee84ab..327a2c4f1d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -60,8 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
uint32_t maxsz = vlmax << sew;
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
(maxsz >= 8);
- flags = FIELD_DP32(flags, TB_FLAGS, VILL,
- FIELD_EX64(env->vtype, VTYPE, VILL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 292f7e1624..b11d92b51b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -283,7 +283,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
static RISCVException read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->vtype;
+ uint64_t vill;
+ switch (env->xl) {
+ case MXL_RV32:
+ vill = (uint32_t)env->vill << 31;
+ break;
+ case MXL_RV64:
+ vill = (uint64_t)env->vill << 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ *val = (target_ulong)vill | env->vtype;
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index a4b7859c2a..740e11fcff 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -124,8 +124,8 @@ static bool vector_needed(void *opaque)
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector = {
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_BOOL(env.vill, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ad505ec9b2..a9484c22ea 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
|| (ediv != 0)
|| (reserved != 0)) {
/* only set vill bit. */
- env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+ env->vill = 1;
+ env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;
--
2.25.1
next prev parent reply other threads:[~2022-01-20 17:04 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-20 12:20 [PATCH v8 00/23] Support UXL filed in xstatus LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 02/23] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 05/23] target/riscv: Create xl field in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 09/23] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 11/23] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-20 12:20 ` LIU Zhiwei [this message]
2022-01-20 12:20 ` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 18/23] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 19/23] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor LIU Zhiwei
2022-01-20 21:25 ` Alistair Francis
2022-01-20 12:20 ` [PATCH v8 22/23] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-21 0:03 ` [PATCH v8 00/23] Support UXL filed in xstatus Alistair Francis
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