From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: guoren@linux.alibaba.com, bin.meng@windriver.com,
richard.henderson@linaro.org, palmer@dabbelt.com,
Alistair Francis <alistair.francis@wdc.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v8 19/23] target/riscv: Adjust vector address with mask
Date: Thu, 20 Jan 2022 20:20:46 +0800 [thread overview]
Message-ID: <20220120122050.41546-20-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20220120122050.41546-1-zhiwei_liu@c-sky.com>
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index efb3129532..020d2e841f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -139,6 +139,11 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
return scale < 0 ? vlenb >> -scale : vlenb << scale;
}
+static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
+{
+ return (addr & env->cur_pmmask) | env->cur_pmbase;
+}
+
/*
* This function checks watchpoint before real load operation.
*
@@ -156,12 +161,12 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
target_ulong pagelen = -(addr | TARGET_PAGE_MASK);
target_ulong curlen = MIN(pagelen, len);
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
if (len > curlen) {
addr += curlen;
curlen = len - curlen;
- probe_access(env, addr, curlen, access_type,
+ probe_access(env, adjust_addr(env, addr), curlen, access_type,
cpu_mmu_index(env, false), ra);
}
}
@@ -239,7 +244,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
k = 0;
while (k < nf) {
target_ulong addr = base + stride * i + (k << esz);
- ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
}
}
@@ -295,7 +300,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k = 0;
while (k < nf) {
target_ulong addr = base + ((i * nf + k) << esz);
- ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
}
}
@@ -409,7 +414,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
k = 0;
while (k < nf) {
abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
- ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
}
}
@@ -488,7 +493,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- addr = base + i * (nf << esz);
+ addr = adjust_addr(env, base + i * (nf << esz));
if (i == 0) {
probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
} else {
@@ -515,7 +520,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
break;
}
remain -= offset;
- addr += offset;
+ addr = adjust_addr(env, addr + offset);
}
}
}
@@ -531,7 +536,7 @@ ProbeSuccess:
}
while (k < nf) {
target_ulong addr = base + ((i * nf + k) << esz);
- ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
k++;
}
}
@@ -585,7 +590,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
/* load/store rest of elements of current segment pointed by vstart */
for (pos = off; pos < max_elems; pos++, env->vstart++) {
target_ulong addr = base + ((pos + k * max_elems) << esz);
- ldst_elem(env, addr, pos + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, ra);
}
k++;
}
@@ -594,7 +599,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
for (; k < nf; k++) {
for (i = 0; i < max_elems; i++, env->vstart++) {
target_ulong addr = base + ((i + k * max_elems) << esz);
- ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ ldst_elem(env, adjust_addr(env, addr), i + k * max_elems, vd, ra);
}
}
--
2.25.1
next prev parent reply other threads:[~2022-01-20 17:12 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-20 12:20 [PATCH v8 00/23] Support UXL filed in xstatus LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 02/23] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 05/23] target/riscv: Create xl field in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 07/23] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 09/23] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 11/23] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 13/23] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 15/23] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 18/23] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-20 12:20 ` LIU Zhiwei [this message]
2022-01-20 12:20 ` [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor LIU Zhiwei
2022-01-20 21:25 ` Alistair Francis
2022-01-20 12:20 ` [PATCH v8 22/23] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-20 12:20 ` [PATCH v8 23/23] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-21 0:03 ` [PATCH v8 00/23] Support UXL filed in xstatus Alistair Francis
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