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envelope-from=prvs=0135fdaf6=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-2-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 4 ++++ target/riscv/cpu_helper.c | 5 ++++- target/riscv/csr.c | 6 +++++- target/riscv/translate.c | 2 ++ 5 files changed, 16 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 22c94d3c57..424bdcc7fa 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -340,6 +340,7 @@ struct RISCVCPU { bool ext_icsr; bool ext_zfh; bool ext_zfhmin; + bool ext_zve64f; =20 char *priv_spec; char *user_spec; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 32879f1403..cdb893d601 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -609,6 +609,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } set_vext_version(env, vext_version); } + if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) { + error_setg(errp, "Zve64f extension depends upon RVF."); + return; + } if (cpu->cfg.ext_j) { ext |=3D RVJ; } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 434a83e66a..43d498aae1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -69,12 +69,15 @@ static RISCVMXL cpu_get_xl(CPURISCVState *env) void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + uint32_t flags =3D 0; =20 *pc =3D env->pc; *cs_base =3D 0; =20 - if (riscv_has_ext(env, RVV)) { + if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) { /* * If env->vl equals to VLMAX, we can use generic vector operati= on * expanders (GVEC) to accerlate the vector operations. diff --git a/target/riscv/csr.c b/target/riscv/csr.c index adb3d4381d..e9311cfd9d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -47,7 +47,11 @@ static RISCVException fs(CPURISCVState *env, int csrno= ) =20 static RISCVException vs(CPURISCVState *env, int csrno) { - if (env->misa_ext & RVV) { + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (env->misa_ext & RVV || + cpu->cfg.ext_zve64f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 615048ec87..d3c0d44e2e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -79,6 +79,7 @@ typedef struct DisasContext { bool ext_ifencei; bool ext_zfh; bool ext_zfhmin; + bool ext_zve64f; bool hlsx; /* vector extension */ bool vill; @@ -894,6 +895,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->ext_zfh =3D cpu->cfg.ext_zfh; ctx->ext_zfhmin =3D cpu->cfg.ext_zfhmin; + ctx->ext_zve64f =3D cpu->cfg.ext_zve64f; ctx->vlen =3D cpu->cfg.vlen; ctx->elen =3D cpu->cfg.elen; ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS)= ; --=20 2.31.1