From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <apatel@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios
Date: Fri, 21 Jan 2022 15:58:05 +1000 [thread overview]
Message-ID: <20220121055830.3164408-37-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com>
From: Anup Patel <apatel@ventanamicro.com>
Currently, we have to use OpenSBI firmware ELF as bios for the spike
machine because the HTIF console requires ELF for parsing "fromhost"
and "tohost" symbols.
The latest OpenSBI can now optionally pick-up HTIF register address
from HTIF DT node so using this feature spike machine can now use
OpenSBI firmware BIN as bios.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/char/riscv_htif.h | 5 ++++-
include/hw/riscv/spike.h | 1 +
hw/char/riscv_htif.c | 33 +++++++++++++++++++----------
hw/riscv/spike.c | 41 ++++++++++++++++++++++--------------
4 files changed, 52 insertions(+), 28 deletions(-)
diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index fb9452cf51..f888ac1b30 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -52,8 +52,11 @@ extern const MemoryRegionOps htif_io_ops;
void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
uint64_t st_size);
+/* Check if HTIF uses ELF symbols */
+bool htif_uses_elf_symbols(void);
+
/* legacy pre qom */
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
- CPURISCVState *env, Chardev *chr);
+ CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
#endif
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index cdd1a13011..73d69234de 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -43,6 +43,7 @@ struct SpikeState {
enum {
SPIKE_MROM,
+ SPIKE_HTIF,
SPIKE_CLINT,
SPIKE_DRAM
};
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index ddae738d56..729edbf968 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -228,13 +228,25 @@ static const MemoryRegionOps htif_mm_ops = {
.write = htif_mm_write,
};
+bool htif_uses_elf_symbols(void)
+{
+ return (address_symbol_set == 3) ? true : false;
+}
+
HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
- CPURISCVState *env, Chardev *chr)
+ CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
{
- uint64_t base = MIN(tohost_addr, fromhost_addr);
- uint64_t size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
- uint64_t tohost_offset = tohost_addr - base;
- uint64_t fromhost_offset = fromhost_addr - base;
+ uint64_t base, size, tohost_offset, fromhost_offset;
+
+ if (!htif_uses_elf_symbols()) {
+ fromhost_addr = nonelf_base;
+ tohost_addr = nonelf_base + 8;
+ }
+
+ base = MIN(tohost_addr, fromhost_addr);
+ size = MAX(tohost_addr + 8, fromhost_addr + 8) - base;
+ tohost_offset = tohost_addr - base;
+ fromhost_offset = fromhost_addr - base;
HTIFState *s = g_malloc0(sizeof(HTIFState));
s->address_space = address_space;
@@ -249,12 +261,11 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
qemu_chr_fe_init(&s->chr, chr, &error_abort);
qemu_chr_fe_set_handlers(&s->chr, htif_can_recv, htif_recv, htif_event,
htif_be_change, s, NULL, true);
- if (address_symbol_set == 3) {
- memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
- TYPE_HTIF_UART, size);
- memory_region_add_subregion_overlap(address_space, base,
- &s->mmio, 1);
- }
+
+ memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
+ TYPE_HTIF_UART, size);
+ memory_region_add_subregion_overlap(address_space, base,
+ &s->mmio, 1);
return s;
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 288d69cd9f..597df4c288 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -42,6 +42,7 @@
static const MemMapEntry spike_memmap[] = {
[SPIKE_MROM] = { 0x1000, 0xf000 },
+ [SPIKE_HTIF] = { 0x1000000, 0x1000 },
[SPIKE_CLINT] = { 0x2000000, 0x10000 },
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
@@ -75,6 +76,10 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/htif");
qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
+ if (!htif_uses_elf_symbols()) {
+ qemu_fdt_setprop_cells(fdt, "/htif", "reg",
+ 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
+ }
qemu_fdt_add_subnode(fdt, "/soc");
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
@@ -172,6 +177,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
if (cmdline) {
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
}
}
@@ -241,10 +247,6 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
machine->ram);
- /* create device tree */
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
- riscv_is_32bit(&s->soc[0]));
-
/* boot rom */
memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
memmap[SPIKE_MROM].size, &error_fatal);
@@ -266,6 +268,7 @@ static void spike_board_init(MachineState *machine)
htif_symbol_callback);
}
+ /* Load kernel */
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
firmware_end_addr);
@@ -273,17 +276,6 @@ static void spike_board_init(MachineState *machine)
kernel_entry = riscv_load_kernel(machine->kernel_filename,
kernel_start_addr,
htif_symbol_callback);
-
- if (machine->initrd_filename) {
- hwaddr start;
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
- &start);
- qemu_fdt_setprop_cell(s->fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
- end);
- }
} else {
/*
* If dynamic firmware is used, it doesn't know where is the next mode
@@ -292,6 +284,22 @@ static void spike_board_init(MachineState *machine)
kernel_entry = 0;
}
+ /* Create device tree */
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+ riscv_is_32bit(&s->soc[0]));
+
+ /* Load initrd */
+ if (machine->kernel_filename && machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
+
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, s->fdt);
@@ -303,7 +311,8 @@ static void spike_board_init(MachineState *machine)
/* initialize HTIF using symbols found in load_kernel */
htif_mm_init(system_memory, mask_rom,
- &s->soc[0].harts[0].env, serial_hd(0));
+ &s->soc[0].harts[0].env, serial_hd(0),
+ memmap[SPIKE_HTIF].base);
}
static void spike_machine_instance_init(Object *obj)
--
2.31.1
next prev parent reply other threads:[~2022-01-21 8:46 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-21 5:57 [PULL 00/61] riscv-to-apply queue Alistair Francis
2022-01-21 5:57 ` [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register Alistair Francis
2022-01-21 5:57 ` [PULL 02/61] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-21 5:57 ` [PULL 03/61] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-21 5:57 ` [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h Alistair Francis
2022-01-21 5:57 ` [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Alistair Francis
2022-01-21 5:57 ` [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu Alistair Francis
2022-01-21 5:57 ` [PULL 07/61] target/riscv: Implement kvm_arch_get_registers Alistair Francis
2022-01-21 5:57 ` [PULL 08/61] target/riscv: Implement kvm_arch_put_registers Alistair Francis
2022-01-21 5:57 ` [PULL 09/61] target/riscv: Support start kernel directly by KVM Alistair Francis
2022-01-21 5:57 ` [PULL 10/61] target/riscv: Support setting external interrupt " Alistair Francis
2022-01-21 5:57 ` [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Alistair Francis
2022-01-21 5:57 ` [PULL 12/61] target/riscv: Add host cpu type Alistair Francis
2022-01-21 5:57 ` [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer Alistair Francis
2022-01-21 5:57 ` [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing Alistair Francis
2022-01-21 5:57 ` [PULL 15/61] target/riscv: Support virtual time context synchronization Alistair Francis
2022-01-21 5:57 ` [PULL 16/61] target/riscv: enable riscv kvm accel Alistair Francis
2022-01-21 5:57 ` [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers Alistair Francis
2022-01-21 5:57 ` [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment Alistair Francis
2022-01-21 5:57 ` [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Alistair Francis
2022-01-21 5:57 ` [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns Alistair Francis
2022-01-21 5:57 ` [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns Alistair Francis
2022-01-21 5:57 ` [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Alistair Francis
2022-01-21 5:57 ` [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Alistair Francis
2022-01-21 5:57 ` [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Alistair Francis
2022-01-21 5:57 ` [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Alistair Francis
2022-01-21 5:57 ` [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Alistair Francis
2022-01-21 5:57 ` [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing " Alistair Francis
2022-01-21 5:57 ` [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Alistair Francis
2022-01-21 5:57 ` [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Alistair Francis
2022-01-21 5:57 ` [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns Alistair Francis
2022-01-21 5:58 ` [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Alistair Francis
2022-01-21 5:58 ` [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Alistair Francis
2022-01-21 5:58 ` [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Alistair Francis
2022-01-21 5:58 ` [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing " Alistair Francis
2022-01-21 5:58 ` [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Alistair Francis
2022-01-21 5:58 ` Alistair Francis [this message]
2022-01-21 5:58 ` [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names Alistair Francis
2022-01-21 5:58 ` [PULL 38/61] roms/opensbi: Remove ELF images Alistair Francis
2022-01-21 5:58 ` [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl Alistair Francis
2022-01-21 5:58 ` [PULL 40/61] target/riscv: Don't save pc when exception return Alistair Francis
2022-01-21 5:58 ` [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr Alistair Francis
2022-01-21 5:58 ` [PULL 42/61] target/riscv: Sign extend pc for different XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 43/61] target/riscv: Create xl field in env Alistair Francis
2022-01-21 5:58 ` [PULL 44/61] target/riscv: Ignore the pc bits above XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 45/61] target/riscv: Extend pc for runtime pc write Alistair Francis
2022-01-21 5:58 ` [PULL 46/61] target/riscv: Use gdb xml according to max mxlen Alistair Francis
2022-01-21 5:58 ` [PULL 47/61] target/riscv: Relax debug check for pm write Alistair Francis
2022-01-21 5:58 ` [PULL 48/61] target/riscv: Adjust csr write mask with XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 49/61] target/riscv: Create current pm fields in env Alistair Francis
2022-01-21 5:58 ` [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base] Alistair Francis
2022-01-21 5:58 ` [PULL 51/61] target/riscv: Calculate address according to XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 52/61] target/riscv: Split pm_enabled into mask and base Alistair Francis
2022-01-21 5:58 ` [PULL 53/61] target/riscv: Split out the vill from vtype Alistair Francis
2022-01-28 16:10 ` Peter Maydell
2022-02-01 2:12 ` Alistair Francis
2022-02-01 6:47 ` LIU Zhiwei
2022-01-21 5:58 ` [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 55/61] target/riscv: Remove VILL field in VTYPE Alistair Francis
2022-01-21 5:58 ` [PULL 56/61] target/riscv: Fix check range for first fault only Alistair Francis
2022-01-21 5:58 ` [PULL 57/61] target/riscv: Adjust vector address with mask Alistair Francis
2022-01-21 5:58 ` [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 59/61] target/riscv: Set default XLEN for hypervisor Alistair Francis
2022-01-21 5:58 ` [PULL 60/61] target/riscv: Enable uxl field write Alistair Francis
2022-01-21 5:58 ` [PULL 61/61] target/riscv: Relax UXL field for debugging Alistair Francis
2022-01-21 12:58 ` [PULL 00/61] riscv-to-apply queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220121055830.3164408-37-alistair.francis@opensource.wdc.com \
--to=alistair.francis@opensource.wdc.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=apatel@ventanamicro.com \
--cc=bmeng.cn@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).