From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, LIU Zhiwei <zhiwei_liu@c-sky.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 53/61] target/riscv: Split out the vill from vtype
Date: Fri, 21 Jan 2022 15:58:22 +1000 [thread overview]
Message-ID: <20220121055830.3164408-54-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com>
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c | 3 +--
target/riscv/csr.c | 13 ++++++++++++-
target/riscv/machine.c | 5 +++--
target/riscv/vector_helper.c | 3 ++-
5 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 89621e1996..6c740b92c1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -125,6 +125,7 @@ struct CPURISCVState {
target_ulong vl;
target_ulong vstart;
target_ulong vtype;
+ bool vill;
target_ulong pc;
target_ulong load_res;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 502aee84ab..327a2c4f1d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -60,8 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
uint32_t maxsz = vlmax << sew;
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
(maxsz >= 8);
- flags = FIELD_DP32(flags, TB_FLAGS, VILL,
- FIELD_EX64(env->vtype, VTYPE, VILL));
+ flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
FIELD_EX64(env->vtype, VTYPE, VLMUL));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 292f7e1624..b11d92b51b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -283,7 +283,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
static RISCVException read_vtype(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->vtype;
+ uint64_t vill;
+ switch (env->xl) {
+ case MXL_RV32:
+ vill = (uint32_t)env->vill << 31;
+ break;
+ case MXL_RV64:
+ vill = (uint64_t)env->vill << 63;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ *val = (target_ulong)vill | env->vtype;
return RISCV_EXCP_NONE;
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index a4b7859c2a..740e11fcff 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -124,8 +124,8 @@ static bool vector_needed(void *opaque)
static const VMStateDescription vmstate_vector = {
.name = "cpu/vector",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.needed = vector_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
@@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector = {
VMSTATE_UINTTL(env.vl, RISCVCPU),
VMSTATE_UINTTL(env.vstart, RISCVCPU),
VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_BOOL(env.vill, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ad505ec9b2..a9484c22ea 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
|| (ediv != 0)
|| (reserved != 0)) {
/* only set vill bit. */
- env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+ env->vill = 1;
+ env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;
--
2.31.1
next prev parent reply other threads:[~2022-01-21 9:42 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-21 5:57 [PULL 00/61] riscv-to-apply queue Alistair Francis
2022-01-21 5:57 ` [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register Alistair Francis
2022-01-21 5:57 ` [PULL 02/61] riscv: opentitan: fixup plic stride len Alistair Francis
2022-01-21 5:57 ` [PULL 03/61] hw: timer: ibex_timer: update/add reg address Alistair Francis
2022-01-21 5:57 ` [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h Alistair Francis
2022-01-21 5:57 ` [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Alistair Francis
2022-01-21 5:57 ` [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu Alistair Francis
2022-01-21 5:57 ` [PULL 07/61] target/riscv: Implement kvm_arch_get_registers Alistair Francis
2022-01-21 5:57 ` [PULL 08/61] target/riscv: Implement kvm_arch_put_registers Alistair Francis
2022-01-21 5:57 ` [PULL 09/61] target/riscv: Support start kernel directly by KVM Alistair Francis
2022-01-21 5:57 ` [PULL 10/61] target/riscv: Support setting external interrupt " Alistair Francis
2022-01-21 5:57 ` [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Alistair Francis
2022-01-21 5:57 ` [PULL 12/61] target/riscv: Add host cpu type Alistair Francis
2022-01-21 5:57 ` [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer Alistair Francis
2022-01-21 5:57 ` [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing Alistair Francis
2022-01-21 5:57 ` [PULL 15/61] target/riscv: Support virtual time context synchronization Alistair Francis
2022-01-21 5:57 ` [PULL 16/61] target/riscv: enable riscv kvm accel Alistair Francis
2022-01-21 5:57 ` [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers Alistair Francis
2022-01-21 5:57 ` [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment Alistair Francis
2022-01-21 5:57 ` [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V Alistair Francis
2022-01-21 5:57 ` [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns Alistair Francis
2022-01-21 5:57 ` [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns Alistair Francis
2022-01-21 5:57 ` [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns Alistair Francis
2022-01-21 5:57 ` [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns Alistair Francis
2022-01-21 5:57 ` [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns Alistair Francis
2022-01-21 5:57 ` [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns Alistair Francis
2022-01-21 5:57 ` [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns Alistair Francis
2022-01-21 5:57 ` [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing " Alistair Francis
2022-01-21 5:57 ` [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on Alistair Francis
2022-01-21 5:57 ` [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V Alistair Francis
2022-01-21 5:57 ` [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns Alistair Francis
2022-01-21 5:58 ` [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns Alistair Francis
2022-01-21 5:58 ` [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns Alistair Francis
2022-01-21 5:58 ` [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns Alistair Francis
2022-01-21 5:58 ` [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing " Alistair Francis
2022-01-21 5:58 ` [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on Alistair Francis
2022-01-21 5:58 ` [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios Alistair Francis
2022-01-21 5:58 ` [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names Alistair Francis
2022-01-21 5:58 ` [PULL 38/61] roms/opensbi: Remove ELF images Alistair Francis
2022-01-21 5:58 ` [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl Alistair Francis
2022-01-21 5:58 ` [PULL 40/61] target/riscv: Don't save pc when exception return Alistair Francis
2022-01-21 5:58 ` [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr Alistair Francis
2022-01-21 5:58 ` [PULL 42/61] target/riscv: Sign extend pc for different XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 43/61] target/riscv: Create xl field in env Alistair Francis
2022-01-21 5:58 ` [PULL 44/61] target/riscv: Ignore the pc bits above XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 45/61] target/riscv: Extend pc for runtime pc write Alistair Francis
2022-01-21 5:58 ` [PULL 46/61] target/riscv: Use gdb xml according to max mxlen Alistair Francis
2022-01-21 5:58 ` [PULL 47/61] target/riscv: Relax debug check for pm write Alistair Francis
2022-01-21 5:58 ` [PULL 48/61] target/riscv: Adjust csr write mask with XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 49/61] target/riscv: Create current pm fields in env Alistair Francis
2022-01-21 5:58 ` [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base] Alistair Francis
2022-01-21 5:58 ` [PULL 51/61] target/riscv: Calculate address according to XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 52/61] target/riscv: Split pm_enabled into mask and base Alistair Francis
2022-01-21 5:58 ` Alistair Francis [this message]
2022-01-28 16:10 ` [PULL 53/61] target/riscv: Split out the vill from vtype Peter Maydell
2022-02-01 2:12 ` Alistair Francis
2022-02-01 6:47 ` LIU Zhiwei
2022-01-21 5:58 ` [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 55/61] target/riscv: Remove VILL field in VTYPE Alistair Francis
2022-01-21 5:58 ` [PULL 56/61] target/riscv: Fix check range for first fault only Alistair Francis
2022-01-21 5:58 ` [PULL 57/61] target/riscv: Adjust vector address with mask Alistair Francis
2022-01-21 5:58 ` [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN Alistair Francis
2022-01-21 5:58 ` [PULL 59/61] target/riscv: Set default XLEN for hypervisor Alistair Francis
2022-01-21 5:58 ` [PULL 60/61] target/riscv: Enable uxl field write Alistair Francis
2022-01-21 5:58 ` [PULL 61/61] target/riscv: Relax UXL field for debugging Alistair Francis
2022-01-21 12:58 ` [PULL 00/61] riscv-to-apply queue Peter Maydell
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