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envelope-from=prvs=0135fdaf6=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 3 +-- target/riscv/csr.c | 13 ++++++++++++- target/riscv/machine.c | 5 +++-- target/riscv/vector_helper.c | 3 ++- 5 files changed, 19 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 89621e1996..6c740b92c1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,7 @@ struct CPURISCVState { target_ulong vl; target_ulong vstart; target_ulong vtype; + bool vill; =20 target_ulong pc; target_ulong load_res; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 502aee84ab..327a2c4f1d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -60,8 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, uint32_t maxsz =3D vlmax << sew; bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env= ->vl) && (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, - FIELD_EX64(env->vtype, VTYPE, VILL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 292f7e1624..b11d92b51b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -283,7 +283,18 @@ static RISCVException write_fcsr(CPURISCVState *env,= int csrno, static RISCVException read_vtype(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->vtype; + uint64_t vill; + switch (env->xl) { + case MXL_RV32: + vill =3D (uint32_t)env->vill << 31; + break; + case MXL_RV64: + vill =3D (uint64_t)env->vill << 63; + break; + default: + g_assert_not_reached(); + } + *val =3D (target_ulong)vill | env->vtype; return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index a4b7859c2a..740e11fcff 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -124,8 +124,8 @@ static bool vector_needed(void *opaque) =20 static const VMStateDescription vmstate_vector =3D { .name =3D "cpu/vector", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D vector_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / = 64), @@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector =3D { VMSTATE_UINTTL(env.vl, RISCVCPU), VMSTATE_UINTTL(env.vstart, RISCVCPU), VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_BOOL(env.vill, RISCVCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ad505ec9b2..a9484c22ea 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, || (ediv !=3D 0) || (reserved !=3D 0)) { /* only set vill bit. */ - env->vtype =3D FIELD_DP64(0, VTYPE, VILL, 1); + env->vill =3D 1; + env->vtype =3D 0; env->vl =3D 0; env->vstart =3D 0; return 0; --=20 2.31.1