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envelope-from=prvs=0135fdaf6=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 28 ++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5a6d49aa64..7c87433645 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -449,6 +449,9 @@ typedef enum { #define COUNTEREN_IR (1 << 2) #define COUNTEREN_HPM3 (1 << 3) =20 +/* vsstatus CSR bits */ +#define VSSTATUS64_UXL 0x0000000300000000ULL + /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b11d92b51b..523d07a95e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -496,7 +496,7 @@ static const target_ulong vs_delegable_excps =3D DELE= GABLE_EXCPS & (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_S= PIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL= ; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MI= P_UEIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP |= MIP_VSEIP; @@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, { uint64_t mstatus =3D env->mstatus; uint64_t mask =3D 0; + RISCVMXL xl =3D riscv_cpu_mxl(env); =20 /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | @@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *= env, int csrno, MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW | MSTATUS_VS; =20 - if (riscv_cpu_mxl(env) !=3D MXL_RV32) { + if (xl !=3D MXL_RV32) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ mask |=3D MSTATUS_MPV | MSTATUS_GVA; + if ((val & MSTATUS64_UXL) !=3D 0) { + mask |=3D MSTATUS64_UXL; + } } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 - RISCVMXL xl =3D riscv_cpu_mxl(env); if (xl > MXL_RV32) { - /* SXL and UXL fields are for now read only */ + /* SXL field is for now read only */ mstatus =3D set_field(mstatus, MSTATUS64_SXL, xl); - mstatus =3D set_field(mstatus, MSTATUS64_UXL, xl); } env->mstatus =3D mstatus; env->xl =3D cpu_recompute_xl(env); @@ -898,6 +900,9 @@ static RISCVException read_sstatus_i128(CPURISCVState= *env, int csrno, { uint64_t mask =3D sstatus_v1_10_mask; uint64_t sstatus =3D env->mstatus & mask; + if (env->xl !=3D MXL_RV32) { + mask |=3D SSTATUS64_UXL; + } =20 *val =3D int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); return RISCV_EXCP_NONE; @@ -907,7 +912,9 @@ static RISCVException read_sstatus(CPURISCVState *env= , int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); - + if (env->xl !=3D MXL_RV32) { + mask |=3D SSTATUS64_UXL; + } /* TODO: Use SXL not MXL. */ *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; @@ -917,6 +924,12 @@ static RISCVException write_sstatus(CPURISCVState *e= nv, int csrno, target_ulong val) { target_ulong mask =3D (sstatus_v1_10_mask); + + if (env->xl !=3D MXL_RV32) { + if ((val & SSTATUS64_UXL) !=3D 0) { + mask |=3D SSTATUS64_UXL; + } + } target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -1380,6 +1393,9 @@ static RISCVException write_vsstatus(CPURISCVState = *env, int csrno, target_ulong val) { uint64_t mask =3D (target_ulong)-1; + if ((val & VSSTATUS64_UXL) =3D=3D 0) { + mask &=3D ~VSSTATUS64_UXL; + } env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; return RISCV_EXCP_NONE; } --=20 2.31.1