From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
alistair23@gmail.com, "Bin Meng" <bin.meng@windriver.com>,
palmer@dabbelt.com, "Peter Xu" <peterx@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
bmeng.cn@gmail.com
Subject: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
Date: Mon, 24 Jan 2022 10:59:56 +1000 [thread overview]
Message-ID: <20220124005958.38848-1-alistair.francis@opensource.wdc.com> (raw)
From: Alistair Francis <alistair.francis@wdc.com>
This series adds a MO_ op to specify that a load instruction should
produce a store fault. This is used on RISC-V to produce a store/amo
fault when an atomic access fails.
This fixes: https://gitlab.com/qemu-project/qemu/-/issues/594
Alistair Francis (2):
accel: tcg: Allow forcing a store fault on read ops
targett/riscv: rva: Correctly generate a store/amo fault
include/exec/memop.h | 2 +
accel/tcg/cputlb.c | 11 ++++-
target/riscv/insn_trans/trans_rva.c.inc | 56 ++++++++++++++++---------
3 files changed, 48 insertions(+), 21 deletions(-)
--
2.31.1
next reply other threads:[~2022-01-24 1:04 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 0:59 Alistair Francis [this message]
2022-01-24 0:59 ` [PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops Alistair Francis
2022-01-24 0:59 ` [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault Alistair Francis
2022-01-24 5:38 ` LIU Zhiwei
2022-01-26 9:50 ` Weiwei Li
2022-01-24 5:17 ` [PATCH 0/2] RISC-V: Correctly generate store/amo faults LIU Zhiwei
2022-01-26 0:09 ` Richard Henderson
2022-02-01 4:40 ` Alistair Francis
2022-02-02 0:37 ` Richard Henderson
2022-02-04 7:36 ` Alistair Francis
2022-02-04 20:33 ` Richard Henderson
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