From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
alistair23@gmail.com, "Bin Meng" <bin.meng@windriver.com>,
palmer@dabbelt.com, "Peter Xu" <peterx@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
bmeng.cn@gmail.com
Subject: [PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops
Date: Mon, 24 Jan 2022 10:59:57 +1000 [thread overview]
Message-ID: <20220124005958.38848-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220124005958.38848-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
When performing atomic operations TCG will do a read operation then a
write operation. This results in a MMU_DATA_LOAD fault if the address is
invalid.
For some platforms (such as RISC-V) we should produce a store fault if
an atomic operation fails. This patch adds a new MemOp (MO_WRITE_FAULT)
that allows us to indicate that the operation should produce a
MMU_DATA_STORE access type if the operation faults.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/exec/memop.h | 2 ++
accel/tcg/cputlb.c | 11 +++++++++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 2a885f3917..93ae1b6a2e 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -81,6 +81,8 @@ typedef enum MemOp {
MO_ALIGN_32 = 5 << MO_ASHIFT,
MO_ALIGN_64 = 6 << MO_ASHIFT,
+ MO_WRITE_FAULT = 0x100,
+
/* Combinations of the above, for ease of use. */
MO_UB = MO_8,
MO_UW = MO_16,
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 5e0d0eebc3..320555d5e9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1362,8 +1362,15 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
section->offset_within_address_space -
section->offset_within_region;
- cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type,
- mmu_idx, iotlbentry->attrs, r, retaddr);
+ if (op & MO_WRITE_FAULT) {
+ cpu_transaction_failed(cpu, physaddr, addr, memop_size(op),
+ MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,
+ r, retaddr);
+ } else {
+ cpu_transaction_failed(cpu, physaddr, addr, memop_size(op),
+ access_type, mmu_idx, iotlbentry->attrs,
+ r, retaddr);
+ }
}
if (locked) {
qemu_mutex_unlock_iothread();
--
2.31.1
next prev parent reply other threads:[~2022-01-24 1:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 0:59 [PATCH 0/2] RISC-V: Correctly generate store/amo faults Alistair Francis
2022-01-24 0:59 ` Alistair Francis [this message]
2022-01-24 0:59 ` [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault Alistair Francis
2022-01-24 5:38 ` LIU Zhiwei
2022-01-26 9:50 ` Weiwei Li
2022-01-24 5:17 ` [PATCH 0/2] RISC-V: Correctly generate store/amo faults LIU Zhiwei
2022-01-26 0:09 ` Richard Henderson
2022-02-01 4:40 ` Alistair Francis
2022-02-02 0:37 ` Richard Henderson
2022-02-04 7:36 ` Alistair Francis
2022-02-04 20:33 ` Richard Henderson
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