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envelope-from=prvs=01678aa48=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis When performing atomic operations TCG will do a read operation then a write operation. This results in a MMU_DATA_LOAD fault if the address is invalid. For some platforms (such as RISC-V) we should produce a store fault if an atomic operation fails. This patch adds a new MemOp (MO_WRITE_FAULT) that allows us to indicate that the operation should produce a MMU_DATA_STORE access type if the operation faults. Signed-off-by: Alistair Francis --- include/exec/memop.h | 2 ++ accel/tcg/cputlb.c | 11 +++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 2a885f3917..93ae1b6a2e 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -81,6 +81,8 @@ typedef enum MemOp { MO_ALIGN_32 =3D 5 << MO_ASHIFT, MO_ALIGN_64 =3D 6 << MO_ASHIFT, =20 + MO_WRITE_FAULT =3D 0x100, + /* Combinations of the above, for ease of use. */ MO_UB =3D MO_8, MO_UW =3D MO_16, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5e0d0eebc3..320555d5e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1362,8 +1362,15 @@ static uint64_t io_readx(CPUArchState *env, CPUIOT= LBEntry *iotlbentry, section->offset_within_address_space - section->offset_within_region; =20 - cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), acce= ss_type, - mmu_idx, iotlbentry->attrs, r, retaddr); + if (op & MO_WRITE_FAULT) { + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->= attrs, + r, retaddr); + } else { + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), + access_type, mmu_idx, iotlbentry->att= rs, + r, retaddr); + } } if (locked) { qemu_mutex_unlock_iothread(); --=20 2.31.1