From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
alistair23@gmail.com, "Bin Meng" <bin.meng@windriver.com>,
palmer@dabbelt.com, "Peter Xu" <peterx@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
bmeng.cn@gmail.com
Subject: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
Date: Mon, 24 Jan 2022 10:59:58 +1000 [thread overview]
Message-ID: <20220124005958.38848-3-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220124005958.38848-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
If the atomic operation fails we want to generate a MMU_DATA_STORE
access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for
the guest.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rva.c.inc | 56 ++++++++++++++++---------
1 file changed, 37 insertions(+), 19 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 45db82c9be..be5c94803b 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -93,7 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
+ return gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
}
static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
@@ -105,55 +105,64 @@ static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
REQUIRE_EXT(ctx, RVA);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TESL));
}
static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
@@ -171,53 +180,62 @@ static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
{
REQUIRE_64BIT(ctx);
- return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEUQ));
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl,
+ (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ));
}
--
2.31.1
next prev parent reply other threads:[~2022-01-24 1:04 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 0:59 [PATCH 0/2] RISC-V: Correctly generate store/amo faults Alistair Francis
2022-01-24 0:59 ` [PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops Alistair Francis
2022-01-24 0:59 ` Alistair Francis [this message]
2022-01-24 5:38 ` [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault LIU Zhiwei
2022-01-26 9:50 ` Weiwei Li
2022-01-24 5:17 ` [PATCH 0/2] RISC-V: Correctly generate store/amo faults LIU Zhiwei
2022-01-26 0:09 ` Richard Henderson
2022-02-01 4:40 ` Alistair Francis
2022-02-02 0:37 ` Richard Henderson
2022-02-04 7:36 ` Alistair Francis
2022-02-04 20:33 ` Richard Henderson
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