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envelope-from=prvs=01678aa48=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis If the atomic operation fails we want to generate a MMU_DATA_STORE access type so we can produce a RISCV_EXCP_STORE_AMO_ACCESS_FAULT for the guest. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594 Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rva.c.inc | 56 ++++++++++++++++--------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_= trans/trans_rva.c.inc index 45db82c9be..be5c94803b 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -93,7 +93,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, static bool trans_lr_w(DisasContext *ctx, arg_lr_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); + return gen_lr(ctx, a, (MO_ALIGN | MO_TESL)); } =20 static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a) @@ -105,55 +105,64 @@ static bool trans_sc_w(DisasContext *ctx, arg_sc_w = *a) static bool trans_amoswap_w(DisasContext *ctx, arg_amoswap_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESL)= ); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoadd_w(DisasContext *ctx, arg_amoadd_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_= TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoxor_w(DisasContext *ctx, arg_amoxor_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_= TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoand_w(DisasContext *ctx, arg_amoand_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_= TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amoor_w(DisasContext *ctx, arg_amoor_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_T= ESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amomin_w(DisasContext *ctx, arg_amomin_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO= _TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amomax_w(DisasContext *ctx, arg_amomax_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO= _TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amominu_w(DisasContext *ctx, arg_amominu_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO= _TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a) { REQUIRE_EXT(ctx, RVA); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO= _TESL)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TESL)); } =20 static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a) @@ -171,53 +180,62 @@ static bool trans_sc_d(DisasContext *ctx, arg_sc_d = *a) static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEUQ)= ); + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_= TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_= TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_= TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_T= EUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO= _TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO= _TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO= _TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } =20 static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a) { REQUIRE_64BIT(ctx); - return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO= _TEUQ)); + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, + (MO_ALIGN | MO_WRITE_FAULT | MO_TEUQ)); } --=20 2.31.1