From: Weiwei Li <liweiwei@iscas.ac.cn>
To: anup@brainfault.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com, ren_guo@c-sky.com
Subject: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
Date: Tue, 25 Jan 2022 14:45:33 +0800 [thread overview]
Message-ID: <20220125064536.7869-3-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220125064536.7869-1-liweiwei@iscas.ac.cn>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2a921bedfd..a5bf07ccb6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -641,6 +641,9 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
+ if (pte & (PTE_D | PTE_A | PTE_U)) {
+ return TRANSLATE_FAIL;
+ }
base = ppn << PGSHIFT;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
--
2.17.1
next prev parent reply other threads:[~2022-01-25 7:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-25 6:45 [PATCH v6 0/5] support subsets of virtual memory extension Weiwei Li
2022-01-25 6:45 ` [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64 Weiwei Li
2022-01-25 8:13 ` LIU Zhiwei
2022-01-25 8:40 ` Guo Ren
2022-01-25 8:54 ` LIU Zhiwei
2022-01-25 9:00 ` Guo Ren
2022-01-25 9:44 ` Weiwei Li
2022-01-28 3:56 ` Guo Ren
2022-01-25 6:45 ` Weiwei Li [this message]
2022-01-28 5:40 ` [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-01-28 7:37 ` Weiwei Li
2022-01-25 6:45 ` [PATCH v6 3/5] target/riscv: add support for svnapot extension Weiwei Li
2022-01-25 6:45 ` [PATCH v6 4/5] target/riscv: add support for svinval extension Weiwei Li
2022-01-25 6:45 ` [PATCH v6 5/5] target/riscv: add support for svpbmt extension Weiwei Li
2022-01-25 8:42 ` [PATCH v6 0/5] support subsets of virtual memory extension Guo Ren
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