[PATCH v6 0/5] support subsets of virtual memory extension

[PATCH v6 0/5] support subsets of virtual memory extension

[Weiwei Li]

This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0. 

Specification:
https://github.com/riscv/virtual-memory/tree/main/specs

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v6

To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.

This implementation can pass the riscv-tests for rv64ssvnapot.

v6:
* select ppn mask base on sxl

v5:
* merge patch https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
* relax pte attribute check

v4:
* fix encodings for hinval_vvma and hinval_gvma
* partition inner PTE check into several steps
* improve commit messages to describe changes

v3:
* drop "x-" in exposed properties

v2:
* add extension check for svnapot and svpbmt

Guo Ren (1):
  target/riscv: Ignore reserved bits in PTE for RV64

Weiwei Li (4):
  target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
  target/riscv: add support for svnapot extension
  target/riscv: add support for svinval extension
  target/riscv: add support for svpbmt extension

 target/riscv/cpu.c                          |  4 ++
 target/riscv/cpu.h                          | 14 ++++
 target/riscv/cpu_bits.h                     | 10 +++
 target/riscv/cpu_helper.c                   | 34 +++++++++-
 target/riscv/insn32.decode                  |  7 ++
 target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
 target/riscv/translate.c                    |  1 +
 7 files changed, 142 insertions(+), 3 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc

-- 
2.17.1

[PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Weiwei Li]

From: Guo Ren <ren_guo@c-sky.com>

Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 13 +++++++++++++
 target/riscv/cpu_bits.h   |  7 +++++++
 target/riscv/cpu_helper.c | 14 +++++++++++++-
 3 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 55635d68d5..45de8faaca 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -341,6 +341,8 @@ struct RISCVCPU {
         bool ext_counters;
         bool ext_ifencei;
         bool ext_icsr;
+        bool ext_svnapot;
+        bool ext_svpbmt;
         bool ext_zfh;
         bool ext_zfhmin;
         bool ext_zve32f;
@@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
     return 16 << env->xl;
 }
 
+#ifndef CONFIG_USER_ONLY
+#ifdef TARGET_RISCV32
+#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+{
+    return get_field(env->mstatus, MSTATUS64_SXL);
+}
+#endif
+#endif
+
 /*
  * Encode LMUL to lmul as follows:
  *     LMUL    vlmul    lmul
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7c87433645..37b622fbfa 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -493,6 +493,13 @@ typedef enum {
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
 
+/* Page table PPN mask */
+#if defined(TARGET_RISCV32)
+#define PTE_PPN_MASK        0xFFFFFC00UL
+#elif defined(TARGET_RISCV64)
+#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
+#endif
+
 /* Leaf page shift amount */
 #define PGSHIFT             12
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 327a2c4f1d..2a921bedfd 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -622,7 +622,19 @@ restart:
             return TRANSLATE_FAIL;
         }
 
-        hwaddr ppn = pte >> PTE_PPN_SHIFT;
+        hwaddr ppn;
+        RISCVCPU *cpu = env_archcpu(env);
+
+        if (riscv_cpu_sxl(env) == MXL_RV32) {
+            ppn = pte >> PTE_PPN_SHIFT;
+        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
+            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
+        } else {
+            ppn = pte >> PTE_PPN_SHIFT;
+            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
+                return TRANSLATE_FAIL;
+            }
+        }
 
         if (!(pte & PTE_V)) {
             /* Invalid PTE */
-- 
2.17.1

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[LIU Zhiwei]

On 2022/1/25 14:45, Weiwei Li wrote:
> From: Guo Ren <ren_guo@c-sky.com>
>
> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>     4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>     4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
>
> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
> Cc: Bin Meng <bmeng.cn@gmail.com>
> Cc: Alistair Francis <alistair.francis@wdc.com>
> ---
>   target/riscv/cpu.h        | 13 +++++++++++++
>   target/riscv/cpu_bits.h   |  7 +++++++
>   target/riscv/cpu_helper.c | 14 +++++++++++++-
>   3 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 55635d68d5..45de8faaca 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -341,6 +341,8 @@ struct RISCVCPU {
>           bool ext_counters;
>           bool ext_ifencei;
>           bool ext_icsr;
> +        bool ext_svnapot;
> +        bool ext_svpbmt;
>           bool ext_zfh;
>           bool ext_zfhmin;
>           bool ext_zve32f;
> @@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
>       return 16 << env->xl;
>   }
>   
> +#ifndef CONFIG_USER_ONLY
> +#ifdef TARGET_RISCV32
> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> +#else
> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> +{
> +    return get_field(env->mstatus, MSTATUS64_SXL);
> +}
> +#endif
> +#endif
> +

Perhaps an interface also works for user mode is better.

+#ifdef TARGET_RISCV32
+#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+{
+#ifdef CONFIG_USER_ONLY
+    return env->misa_mxl;
+#else
+    return get_field(env->mstatus, MSTATUS64_SXL);
+#endif
+}
+#endif
+

>   /*
>    * Encode LMUL to lmul as follows:
>    *     LMUL    vlmul    lmul
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 7c87433645..37b622fbfa 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -493,6 +493,13 @@ typedef enum {
>   /* Page table PPN shift amount */
>   #define PTE_PPN_SHIFT       10
>   
> +/* Page table PPN mask */
> +#if defined(TARGET_RISCV32)
> +#define PTE_PPN_MASK        0xFFFFFC00UL
> +#elif defined(TARGET_RISCV64)
> +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
> +#endif
> +

No need to define PTE_PPN_MASK for TARGET_RISCV32.

>   /* Leaf page shift amount */
>   #define PGSHIFT             12
>   
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 327a2c4f1d..2a921bedfd 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -622,7 +622,19 @@ restart:
>               return TRANSLATE_FAIL;
>           }
>   
> -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
> +        hwaddr ppn;
> +        RISCVCPU *cpu = env_archcpu(env);
> +
> +        if (riscv_cpu_sxl(env) == MXL_RV32) {
> +            ppn = pte >> PTE_PPN_SHIFT;
> +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
> +            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> +        } else {
> +            ppn = pte >> PTE_PPN_SHIFT;
> +            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
> +                return TRANSLATE_FAIL;
> +            }
> +        }
>   
>           if (!(pte & PTE_V)) {
>               /* Invalid PTE */

Otherwise,

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Thanks,
Zhiwei

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Guo Ren]

On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2022/1/25 14:45, Weiwei Li wrote:
> > From: Guo Ren <ren_guo@c-sky.com>
> >
> > Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> > need to ignore them. They cannot be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >     4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >     4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >
> > 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
> >
> > Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> > Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
> > Cc: Bin Meng <bmeng.cn@gmail.com>
> > Cc: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >   target/riscv/cpu.h        | 13 +++++++++++++
> >   target/riscv/cpu_bits.h   |  7 +++++++
> >   target/riscv/cpu_helper.c | 14 +++++++++++++-
> >   3 files changed, 33 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 55635d68d5..45de8faaca 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -341,6 +341,8 @@ struct RISCVCPU {
> >           bool ext_counters;
> >           bool ext_ifencei;
> >           bool ext_icsr;
> > +        bool ext_svnapot;
> > +        bool ext_svpbmt;
> >           bool ext_zfh;
> >           bool ext_zfhmin;
> >           bool ext_zve32f;
> > @@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
> >       return 16 << env->xl;
> >   }
> >
> > +#ifndef CONFIG_USER_ONLY
> > +#ifdef TARGET_RISCV32
> > +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> > +#else
> > +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> > +{
> > +    return get_field(env->mstatus, MSTATUS64_SXL);
> > +}
> > +#endif
> > +#endif
> > +
>
> Perhaps an interface also works for user mode is better.
>
> +#ifdef TARGET_RISCV32
> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> +#else
> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> +{
> +#ifdef CONFIG_USER_ONLY
> +    return env->misa_mxl;
> +#else
> +    return get_field(env->mstatus, MSTATUS64_SXL);
> +#endif
> +}
> +#endif
> +
>
> >   /*
> >    * Encode LMUL to lmul as follows:
> >    *     LMUL    vlmul    lmul
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 7c87433645..37b622fbfa 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -493,6 +493,13 @@ typedef enum {
> >   /* Page table PPN shift amount */
> >   #define PTE_PPN_SHIFT       10
> >
> > +/* Page table PPN mask */
> > +#if defined(TARGET_RISCV32)
> > +#define PTE_PPN_MASK        0xFFFFFC00UL
> > +#elif defined(TARGET_RISCV64)
> > +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
> > +#endif
> > +
>
> No need to define PTE_PPN_MASK for TARGET_RISCV32.

ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;

pte is target_ulong, so types are different.

TARGET_RISCV32: is 32bit.
TARGET_RISCV64: is 64bit.

>
> >   /* Leaf page shift amount */
> >   #define PGSHIFT             12
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 327a2c4f1d..2a921bedfd 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -622,7 +622,19 @@ restart:
> >               return TRANSLATE_FAIL;
> >           }
> >
> > -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
> > +        hwaddr ppn;
> > +        RISCVCPU *cpu = env_archcpu(env);
> > +
> > +        if (riscv_cpu_sxl(env) == MXL_RV32) {
> > +            ppn = pte >> PTE_PPN_SHIFT;
> > +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
> > +            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> > +        } else {
> > +            ppn = pte >> PTE_PPN_SHIFT;
> > +            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
> > +                return TRANSLATE_FAIL;
> > +            }
> > +        }
> >
> >           if (!(pte & PTE_V)) {
> >               /* Invalid PTE */
>
> Otherwise,
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>
> Thanks,
> Zhiwei
>
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[LIU Zhiwei]

On 2022/1/25 16:40, Guo Ren wrote:
> On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>
>> On 2022/1/25 14:45, Weiwei Li wrote:
>>> From: Guo Ren <ren_guo@c-sky.com>
>>>
>>> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
>>> need to ignore them. They cannot be a part of ppn.
>>>
>>> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>>>      4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>>>      4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>>>
>>> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
>>>
>>> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
>>> Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
>>> Cc: Bin Meng <bmeng.cn@gmail.com>
>>> Cc: Alistair Francis <alistair.francis@wdc.com>
>>> ---
>>>    target/riscv/cpu.h        | 13 +++++++++++++
>>>    target/riscv/cpu_bits.h   |  7 +++++++
>>>    target/riscv/cpu_helper.c | 14 +++++++++++++-
>>>    3 files changed, 33 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>> index 55635d68d5..45de8faaca 100644
>>> --- a/target/riscv/cpu.h
>>> +++ b/target/riscv/cpu.h
>>> @@ -341,6 +341,8 @@ struct RISCVCPU {
>>>            bool ext_counters;
>>>            bool ext_ifencei;
>>>            bool ext_icsr;
>>> +        bool ext_svnapot;
>>> +        bool ext_svpbmt;
>>>            bool ext_zfh;
>>>            bool ext_zfhmin;
>>>            bool ext_zve32f;
>>> @@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
>>>        return 16 << env->xl;
>>>    }
>>>
>>> +#ifndef CONFIG_USER_ONLY
>>> +#ifdef TARGET_RISCV32
>>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
>>> +#else
>>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
>>> +{
>>> +    return get_field(env->mstatus, MSTATUS64_SXL);
>>> +}
>>> +#endif
>>> +#endif
>>> +
>> Perhaps an interface also works for user mode is better.
>>
>> +#ifdef TARGET_RISCV32
>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
>> +#else
>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
>> +{
>> +#ifdef CONFIG_USER_ONLY
>> +    return env->misa_mxl;
>> +#else
>> +    return get_field(env->mstatus, MSTATUS64_SXL);
>> +#endif
>> +}
>> +#endif
>> +
>>
>>>    /*
>>>     * Encode LMUL to lmul as follows:
>>>     *     LMUL    vlmul    lmul
>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>>> index 7c87433645..37b622fbfa 100644
>>> --- a/target/riscv/cpu_bits.h
>>> +++ b/target/riscv/cpu_bits.h
>>> @@ -493,6 +493,13 @@ typedef enum {
>>>    /* Page table PPN shift amount */
>>>    #define PTE_PPN_SHIFT       10
>>>
>>> +/* Page table PPN mask */
>>> +#if defined(TARGET_RISCV32)
>>> +#define PTE_PPN_MASK        0xFFFFFC00UL
>>> +#elif defined(TARGET_RISCV64)
>>> +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
>>> +#endif
>>> +
>> No need to define PTE_PPN_MASK for TARGET_RISCV32.
> ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>
> pte is target_ulong, so types are different.
>
> TARGET_RISCV32: is 32bit.
> TARGET_RISCV64: is 64bit.
>
I should make it more clear.  You will not use PTE_PPN_MASK on 
TARGET_RISCV32.
>>>    /* Leaf page shift amount */
>>>    #define PGSHIFT             12
>>>
>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>>> index 327a2c4f1d..2a921bedfd 100644
>>> --- a/target/riscv/cpu_helper.c
>>> +++ b/target/riscv/cpu_helper.c
>>> @@ -622,7 +622,19 @@ restart:
>>>                return TRANSLATE_FAIL;
>>>            }
>>>
>>> -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
>>> +        hwaddr ppn;
>>> +        RISCVCPU *cpu = env_archcpu(env);
>>> +
>>> +        if (riscv_cpu_sxl(env) == MXL_RV32) {
>>> +            ppn = pte >> PTE_PPN_SHIFT;

TARGET_RISCV32 will always come here. So no need to define PTE_PPN_MASK 
for TARGET_RISCV32.

Thanks,
Zhiwei

>>> +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
>>> +            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>>> +        } else {
>>> +            ppn = pte >> PTE_PPN_SHIFT;
>>> +            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
>>> +                return TRANSLATE_FAIL;
>>> +            }
>>> +        }
>>>
>>>            if (!(pte & PTE_V)) {
>>>                /* Invalid PTE */
>> Otherwise,
>>
>> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>>
>> Thanks,
>> Zhiwei
>>
>>
>>
>

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Guo Ren]

On Tue, Jan 25, 2022 at 4:54 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2022/1/25 16:40, Guo Ren wrote:
> > On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> >>
> >> On 2022/1/25 14:45, Weiwei Li wrote:
> >>> From: Guo Ren <ren_guo@c-sky.com>
> >>>
> >>> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> >>> need to ignore them. They cannot be a part of ppn.
> >>>
> >>> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >>>      4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >>>      4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >>>
> >>> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
> >>>
> >>> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> >>> Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
> >>> Cc: Bin Meng <bmeng.cn@gmail.com>
> >>> Cc: Alistair Francis <alistair.francis@wdc.com>
> >>> ---
> >>>    target/riscv/cpu.h        | 13 +++++++++++++
> >>>    target/riscv/cpu_bits.h   |  7 +++++++
> >>>    target/riscv/cpu_helper.c | 14 +++++++++++++-
> >>>    3 files changed, 33 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> >>> index 55635d68d5..45de8faaca 100644
> >>> --- a/target/riscv/cpu.h
> >>> +++ b/target/riscv/cpu.h
> >>> @@ -341,6 +341,8 @@ struct RISCVCPU {
> >>>            bool ext_counters;
> >>>            bool ext_ifencei;
> >>>            bool ext_icsr;
> >>> +        bool ext_svnapot;
> >>> +        bool ext_svpbmt;
> >>>            bool ext_zfh;
> >>>            bool ext_zfhmin;
> >>>            bool ext_zve32f;
> >>> @@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
> >>>        return 16 << env->xl;
> >>>    }
> >>>
> >>> +#ifndef CONFIG_USER_ONLY
> >>> +#ifdef TARGET_RISCV32
> >>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> >>> +#else
> >>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> >>> +{
> >>> +    return get_field(env->mstatus, MSTATUS64_SXL);
> >>> +}
> >>> +#endif
> >>> +#endif
> >>> +
> >> Perhaps an interface also works for user mode is better.
> >>
> >> +#ifdef TARGET_RISCV32
> >> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> >> +#else
> >> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> >> +{
> >> +#ifdef CONFIG_USER_ONLY
> >> +    return env->misa_mxl;
> >> +#else
> >> +    return get_field(env->mstatus, MSTATUS64_SXL);
> >> +#endif
> >> +}
> >> +#endif
> >> +
> >>
> >>>    /*
> >>>     * Encode LMUL to lmul as follows:
> >>>     *     LMUL    vlmul    lmul
> >>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> >>> index 7c87433645..37b622fbfa 100644
> >>> --- a/target/riscv/cpu_bits.h
> >>> +++ b/target/riscv/cpu_bits.h
> >>> @@ -493,6 +493,13 @@ typedef enum {
> >>>    /* Page table PPN shift amount */
> >>>    #define PTE_PPN_SHIFT       10
> >>>
> >>> +/* Page table PPN mask */
> >>> +#if defined(TARGET_RISCV32)
> >>> +#define PTE_PPN_MASK        0xFFFFFC00UL
> >>> +#elif defined(TARGET_RISCV64)
> >>> +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
> >>> +#endif
> >>> +
> >> No need to define PTE_PPN_MASK for TARGET_RISCV32.
> > ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> >
> > pte is target_ulong, so types are different.
> >
> > TARGET_RISCV32: is 32bit.
> > TARGET_RISCV64: is 64bit.
> >
> I should make it more clear.  You will not use PTE_PPN_MASK on
> TARGET_RISCV32.
> >>>    /* Leaf page shift amount */
> >>>    #define PGSHIFT             12
> >>>
> >>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >>> index 327a2c4f1d..2a921bedfd 100644
> >>> --- a/target/riscv/cpu_helper.c
> >>> +++ b/target/riscv/cpu_helper.c
> >>> @@ -622,7 +622,19 @@ restart:
> >>>                return TRANSLATE_FAIL;
> >>>            }
> >>>
> >>> -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
> >>> +        hwaddr ppn;
> >>> +        RISCVCPU *cpu = env_archcpu(env);
> >>> +
> >>> +        if (riscv_cpu_sxl(env) == MXL_RV32) {
> >>> +            ppn = pte >> PTE_PPN_SHIFT;
>
> TARGET_RISCV32 will always come here. So no need to define PTE_PPN_MASK
> for TARGET_RISCV32.
Oops, maybe we should use TARGET_LONG_SIZE == 4

#if TARGET_LONG_SIZE == 4
typedef int32_t target_long;
typedef uint32_t target_ulong;
#define TARGET_FMT_lx "%08x"
#define TARGET_FMT_ld "%d"
#define TARGET_FMT_lu "%u"
#elif TARGET_LONG_SIZE == 8
typedef int64_t target_long;
typedef uint64_t target_ulong;
#define TARGET_FMT_lx "%016" PRIx64
#define TARGET_FMT_ld "%" PRId64
#define TARGET_FMT_lu "%" PRIu64
#else
#error TARGET_LONG_SIZE undefined
#endif

>
> Thanks,
> Zhiwei
>
> >>> +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
> >>> +            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> >>> +        } else {
> >>> +            ppn = pte >> PTE_PPN_SHIFT;
> >>> +            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
> >>> +                return TRANSLATE_FAIL;
> >>> +            }
> >>> +        }
> >>>
> >>>            if (!(pte & PTE_V)) {
> >>>                /* Invalid PTE */
> >> Otherwise,
> >>
> >> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> >>
> >> Thanks,
> >> Zhiwei
> >>
> >>
> >>
> >



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Weiwei Li]

在 2022/1/25 下午5:00, Guo Ren 写道:
> On Tue, Jan 25, 2022 at 4:54 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>
>> On 2022/1/25 16:40, Guo Ren wrote:
>>> On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>>>> On 2022/1/25 14:45, Weiwei Li wrote:
>>>>> From: Guo Ren <ren_guo@c-sky.com>
>>>>>
>>>>> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
>>>>> need to ignore them. They cannot be a part of ppn.
>>>>>
>>>>> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>>>>>       4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>>>>>       4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>>>>>
>>>>> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
>>>>>
>>>>> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
>>>>> Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
>>>>> Cc: Bin Meng <bmeng.cn@gmail.com>
>>>>> Cc: Alistair Francis <alistair.francis@wdc.com>
>>>>> ---
>>>>>     target/riscv/cpu.h        | 13 +++++++++++++
>>>>>     target/riscv/cpu_bits.h   |  7 +++++++
>>>>>     target/riscv/cpu_helper.c | 14 +++++++++++++-
>>>>>     3 files changed, 33 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>>>> index 55635d68d5..45de8faaca 100644
>>>>> --- a/target/riscv/cpu.h
>>>>> +++ b/target/riscv/cpu.h
>>>>> @@ -341,6 +341,8 @@ struct RISCVCPU {
>>>>>             bool ext_counters;
>>>>>             bool ext_ifencei;
>>>>>             bool ext_icsr;
>>>>> +        bool ext_svnapot;
>>>>> +        bool ext_svpbmt;
>>>>>             bool ext_zfh;
>>>>>             bool ext_zfhmin;
>>>>>             bool ext_zve32f;
>>>>> @@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
>>>>>         return 16 << env->xl;
>>>>>     }
>>>>>
>>>>> +#ifndef CONFIG_USER_ONLY
>>>>> +#ifdef TARGET_RISCV32
>>>>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
>>>>> +#else
>>>>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
>>>>> +{
>>>>> +    return get_field(env->mstatus, MSTATUS64_SXL);
>>>>> +}
>>>>> +#endif
>>>>> +#endif
>>>>> +
>>>> Perhaps an interface also works for user mode is better.
>>>>
>>>> +#ifdef TARGET_RISCV32
>>>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
>>>> +#else
>>>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
>>>> +{
>>>> +#ifdef CONFIG_USER_ONLY
>>>> +    return env->misa_mxl;
>>>> +#else
>>>> +    return get_field(env->mstatus, MSTATUS64_SXL);
>>>> +#endif
>>>> +}
>>>> +#endif
>>>> +
>>>>
>>>>>     /*
>>>>>      * Encode LMUL to lmul as follows:
>>>>>      *     LMUL    vlmul    lmul
>>>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
>>>>> index 7c87433645..37b622fbfa 100644
>>>>> --- a/target/riscv/cpu_bits.h
>>>>> +++ b/target/riscv/cpu_bits.h
>>>>> @@ -493,6 +493,13 @@ typedef enum {
>>>>>     /* Page table PPN shift amount */
>>>>>     #define PTE_PPN_SHIFT       10
>>>>>
>>>>> +/* Page table PPN mask */
>>>>> +#if defined(TARGET_RISCV32)
>>>>> +#define PTE_PPN_MASK        0xFFFFFC00UL
>>>>> +#elif defined(TARGET_RISCV64)
>>>>> +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
>>>>> +#endif
>>>>> +
>>>> No need to define PTE_PPN_MASK for TARGET_RISCV32.
>>> ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>>>
>>> pte is target_ulong, so types are different.
>>>
>>> TARGET_RISCV32: is 32bit.
>>> TARGET_RISCV64: is 64bit.
>>>
>> I should make it more clear.  You will not use PTE_PPN_MASK on
>> TARGET_RISCV32.
>>>>>     /* Leaf page shift amount */
>>>>>     #define PGSHIFT             12
>>>>>
>>>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>>>>> index 327a2c4f1d..2a921bedfd 100644
>>>>> --- a/target/riscv/cpu_helper.c
>>>>> +++ b/target/riscv/cpu_helper.c
>>>>> @@ -622,7 +622,19 @@ restart:
>>>>>                 return TRANSLATE_FAIL;
>>>>>             }
>>>>>
>>>>> -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
>>>>> +        hwaddr ppn;
>>>>> +        RISCVCPU *cpu = env_archcpu(env);
>>>>> +
>>>>> +        if (riscv_cpu_sxl(env) == MXL_RV32) {
>>>>> +            ppn = pte >> PTE_PPN_SHIFT;
>> TARGET_RISCV32 will always come here. So no need to define PTE_PPN_MASK
>> for TARGET_RISCV32.
> Oops, maybe we should use TARGET_LONG_SIZE == 4
>
> #if TARGET_LONG_SIZE == 4
> typedef int32_t target_long;
> typedef uint32_t target_ulong;
> #define TARGET_FMT_lx "%08x"
> #define TARGET_FMT_ld "%d"
> #define TARGET_FMT_lu "%u"
> #elif TARGET_LONG_SIZE == 8
> typedef int64_t target_long;
> typedef uint64_t target_ulong;
> #define TARGET_FMT_lx "%016" PRIx64
> #define TARGET_FMT_ld "%" PRId64
> #define TARGET_FMT_lu "%" PRIu64
> #else
> #error TARGET_LONG_SIZE undefined
> #endif
>
TARGET_LONG_SIZE is related to TARGET_RISCV32 and TARGET_RISCV64.

In RV32, the code will truely not reach there when executing. However the code itself have different types for pte and PTE_PPN_MASK, and may cause compiler warning.

So if we only define PTE_PPN_MASK for RV64, maybe we can take type casting here:

   ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;

Regards,
Weiwei Li

>> Thanks,
>> Zhiwei
>>
>>>>> +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
>>>>> +            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>>>>> +        } else {
>>>>> +            ppn = pte >> PTE_PPN_SHIFT;
>>>>> +            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
>>>>> +                return TRANSLATE_FAIL;
>>>>> +            }
>>>>> +        }
>>>>>
>>>>>             if (!(pte & PTE_V)) {
>>>>>                 /* Invalid PTE */
>>>> Otherwise,
>>>>
>>>> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>>>>
>>>> Thanks,
>>>> Zhiwei
>>>>
>>>>
>>>>
>
>

Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64

[Guo Ren]

On Tue, Jan 25, 2022 at 5:49 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
>
> 在 2022/1/25 下午5:00, Guo Ren 写道:
> > On Tue, Jan 25, 2022 at 4:54 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> >>
> >> On 2022/1/25 16:40, Guo Ren wrote:
> >>> On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> >>>> On 2022/1/25 14:45, Weiwei Li wrote:
> >>>>> From: Guo Ren <ren_guo@c-sky.com>
> >>>>>
> >>>>> Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
> >>>>> need to ignore them. They cannot be a part of ppn.
> >>>>>
> >>>>> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >>>>>       4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >>>>>       4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >>>>>
> >>>>> 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
> >>>>>
> >>>>> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> >>>>> Cc: Liu Zhiwei <zhiwei_liu@c-sky.com>
> >>>>> Cc: Bin Meng <bmeng.cn@gmail.com>
> >>>>> Cc: Alistair Francis <alistair.francis@wdc.com>
> >>>>> ---
> >>>>>     target/riscv/cpu.h        | 13 +++++++++++++
> >>>>>     target/riscv/cpu_bits.h   |  7 +++++++
> >>>>>     target/riscv/cpu_helper.c | 14 +++++++++++++-
> >>>>>     3 files changed, 33 insertions(+), 1 deletion(-)
> >>>>>
> >>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> >>>>> index 55635d68d5..45de8faaca 100644
> >>>>> --- a/target/riscv/cpu.h
> >>>>> +++ b/target/riscv/cpu.h
> >>>>> @@ -341,6 +341,8 @@ struct RISCVCPU {
> >>>>>             bool ext_counters;
> >>>>>             bool ext_ifencei;
> >>>>>             bool ext_icsr;
> >>>>> +        bool ext_svnapot;
> >>>>> +        bool ext_svpbmt;
> >>>>>             bool ext_zfh;
> >>>>>             bool ext_zfhmin;
> >>>>>             bool ext_zve32f;
> >>>>> @@ -495,6 +497,17 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
> >>>>>         return 16 << env->xl;
> >>>>>     }
> >>>>>
> >>>>> +#ifndef CONFIG_USER_ONLY
> >>>>> +#ifdef TARGET_RISCV32
> >>>>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> >>>>> +#else
> >>>>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> >>>>> +{
> >>>>> +    return get_field(env->mstatus, MSTATUS64_SXL);
> >>>>> +}
> >>>>> +#endif
> >>>>> +#endif
> >>>>> +
> >>>> Perhaps an interface also works for user mode is better.
> >>>>
> >>>> +#ifdef TARGET_RISCV32
> >>>> +#define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
> >>>> +#else
> >>>> +static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
> >>>> +{
> >>>> +#ifdef CONFIG_USER_ONLY
> >>>> +    return env->misa_mxl;
> >>>> +#else
> >>>> +    return get_field(env->mstatus, MSTATUS64_SXL);
> >>>> +#endif
> >>>> +}
> >>>> +#endif
> >>>> +
> >>>>
> >>>>>     /*
> >>>>>      * Encode LMUL to lmul as follows:
> >>>>>      *     LMUL    vlmul    lmul
> >>>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> >>>>> index 7c87433645..37b622fbfa 100644
> >>>>> --- a/target/riscv/cpu_bits.h
> >>>>> +++ b/target/riscv/cpu_bits.h
> >>>>> @@ -493,6 +493,13 @@ typedef enum {
> >>>>>     /* Page table PPN shift amount */
> >>>>>     #define PTE_PPN_SHIFT       10
> >>>>>
> >>>>> +/* Page table PPN mask */
> >>>>> +#if defined(TARGET_RISCV32)
> >>>>> +#define PTE_PPN_MASK        0xFFFFFC00UL
> >>>>> +#elif defined(TARGET_RISCV64)
> >>>>> +#define PTE_PPN_MASK        0x3FFFFFFFFFFC00ULL
> >>>>> +#endif
> >>>>> +
> >>>> No need to define PTE_PPN_MASK for TARGET_RISCV32.
> >>> ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> >>>
> >>> pte is target_ulong, so types are different.
> >>>
> >>> TARGET_RISCV32: is 32bit.
> >>> TARGET_RISCV64: is 64bit.
> >>>
> >> I should make it more clear.  You will not use PTE_PPN_MASK on
> >> TARGET_RISCV32.
> >>>>>     /* Leaf page shift amount */
> >>>>>     #define PGSHIFT             12
> >>>>>
> >>>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >>>>> index 327a2c4f1d..2a921bedfd 100644
> >>>>> --- a/target/riscv/cpu_helper.c
> >>>>> +++ b/target/riscv/cpu_helper.c
> >>>>> @@ -622,7 +622,19 @@ restart:
> >>>>>                 return TRANSLATE_FAIL;
> >>>>>             }
> >>>>>
> >>>>> -        hwaddr ppn = pte >> PTE_PPN_SHIFT;
> >>>>> +        hwaddr ppn;
> >>>>> +        RISCVCPU *cpu = env_archcpu(env);
> >>>>> +
> >>>>> +        if (riscv_cpu_sxl(env) == MXL_RV32) {
> >>>>> +            ppn = pte >> PTE_PPN_SHIFT;
> >> TARGET_RISCV32 will always come here. So no need to define PTE_PPN_MASK
> >> for TARGET_RISCV32.
> > Oops, maybe we should use TARGET_LONG_SIZE == 4
> >
> > #if TARGET_LONG_SIZE == 4
> > typedef int32_t target_long;
> > typedef uint32_t target_ulong;
> > #define TARGET_FMT_lx "%08x"
> > #define TARGET_FMT_ld "%d"
> > #define TARGET_FMT_lu "%u"
> > #elif TARGET_LONG_SIZE == 8
> > typedef int64_t target_long;
> > typedef uint64_t target_ulong;
> > #define TARGET_FMT_lx "%016" PRIx64
> > #define TARGET_FMT_ld "%" PRId64
> > #define TARGET_FMT_lu "%" PRIu64
> > #else
> > #error TARGET_LONG_SIZE undefined
> > #endif
> >
> TARGET_LONG_SIZE is related to TARGET_RISCV32 and TARGET_RISCV64.
>
> In RV32, the code will truely not reach there when executing. However the code itself have different types for pte and PTE_PPN_MASK, and may cause compiler  warning.
>
> So if we only define PTE_PPN_MASK for RV64, maybe we can take type casting here:
>
>    ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;

 (target_ulong)PTE_PPN_MASK seems (u32) 0x3FFFFFFFFFFC00ULL = 0xFFFFFC00UL

I'm okay with the above.

>
> Regards,
> Weiwei Li
>
> >> Thanks,
> >> Zhiwei
> >>
> >>>>> +        } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
> >>>>> +            ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
> >>>>> +        } else {
> >>>>> +            ppn = pte >> PTE_PPN_SHIFT;
> >>>>> +            if ((pte & ~PTE_PPN_MASK) >> PTE_PPN_SHIFT) {
> >>>>> +                return TRANSLATE_FAIL;
> >>>>> +            }
> >>>>> +        }
> >>>>>
> >>>>>             if (!(pte & PTE_V)) {
> >>>>>                 /* Invalid PTE */
> >>>> Otherwise,
> >>>>
> >>>> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> >>>>
> >>>> Thanks,
> >>>> Zhiwei
> >>>>
> >>>>
> >>>>
> >
> >
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

[PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

[Weiwei Li]

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 target/riscv/cpu_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2a921bedfd..a5bf07ccb6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -641,6 +641,9 @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
+            if (pte & (PTE_D | PTE_A | PTE_U)) {
+                return TRANSLATE_FAIL;
+            }
             base = ppn << PGSHIFT;
         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
             /* Reserved leaf PTE flags: PTE_W */
-- 
2.17.1

Re: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

[Alistair Francis]

On Tue, Jan 25, 2022 at 5:47 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Anup Patel <anup@brainfault.org>

Could you please add a commit message to this patch?

Alistair

> ---
>  target/riscv/cpu_helper.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 2a921bedfd..a5bf07ccb6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -641,6 +641,9 @@ restart:
>              return TRANSLATE_FAIL;
>          } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
>              /* Inner PTE, continue walking */
> +            if (pte & (PTE_D | PTE_A | PTE_U)) {
> +                return TRANSLATE_FAIL;
> +            }
>              base = ppn << PGSHIFT;
>          } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
>              /* Reserved leaf PTE flags: PTE_W */
> --
> 2.17.1
>
>

Re: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

[Weiwei Li]

在 2022/1/28 下午1:40, Alistair Francis 写道:
> On Tue, Jan 25, 2022 at 5:47 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> Reviewed-by: Anup Patel <anup@brainfault.org>
> Could you please add a commit message to this patch?
>
> Alistair

OK. I'll add it.

Regards,

Weiwei Li

>> ---
>>   target/riscv/cpu_helper.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index 2a921bedfd..a5bf07ccb6 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -641,6 +641,9 @@ restart:
>>               return TRANSLATE_FAIL;
>>           } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
>>               /* Inner PTE, continue walking */
>> +            if (pte & (PTE_D | PTE_A | PTE_U)) {
>> +                return TRANSLATE_FAIL;
>> +            }
>>               base = ppn << PGSHIFT;
>>           } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
>>               /* Reserved leaf PTE flags: PTE_W */
>> --
>> 2.17.1
>>
>>

[PATCH v6 3/5] target/riscv: add support for svnapot extension

[Weiwei Li]

- add PTE_N bit
- add PTE_N bit check for inner PTE
- update address translation to support 64KiB continuous region (napot_bits = 4)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 target/riscv/cpu.c        |  2 ++
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c | 17 ++++++++++++++---
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1cb0436187..8752fa1544 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,6 +729,8 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+    DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 37b622fbfa..41190ce985 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -489,6 +489,7 @@ typedef enum {
 #define PTE_A               0x040 /* Accessed */
 #define PTE_D               0x080 /* Dirty */
 #define PTE_SOFT            0x300 /* Reserved for Software */
+#define PTE_N               0x8000000000000000 /* NAPOT translation */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a5bf07ccb6..ef7d9b07bd 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -641,7 +641,7 @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
-            if (pte & (PTE_D | PTE_A | PTE_U)) {
+            if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
                 return TRANSLATE_FAIL;
             }
             base = ppn << PGSHIFT;
@@ -717,8 +717,19 @@ restart:
             /* for superpage mappings, make a fake leaf PTE for the TLB's
                benefit. */
             target_ulong vpn = addr >> PGSHIFT;
-            *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
-                        (addr & ~TARGET_PAGE_MASK);
+
+            int napot_bits = 0;
+            if (cpu->cfg.ext_svnapot && (pte & (target_ulong)PTE_N)) {
+                napot_bits = ctzl(ppn) + 1;
+                if ((i != (levels - 1)) || (napot_bits != 4)) {
+                    return TRANSLATE_FAIL;
+                }
+            }
+
+            *physical = (((ppn & ~(((target_ulong)1 << napot_bits) - 1)) |
+                          (vpn & (((target_ulong)1 << napot_bits) - 1)) |
+                          (vpn & (((target_ulong)1 << ptshift) - 1))
+                        ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK);
 
             /* set permissions on the TLB entry */
             if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
-- 
2.17.1

[PATCH v6 4/5] target/riscv: add support for svinval extension

[Weiwei Li]

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 target/riscv/cpu.c                          |  1 +
 target/riscv/cpu.h                          |  1 +
 target/riscv/insn32.decode                  |  7 ++
 target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
 target/riscv/translate.c                    |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8752fa1544..4efdc16780 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,6 +729,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
+    DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
 
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 45de8faaca..2efe987248 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -341,6 +341,7 @@ struct RISCVCPU {
         bool ext_counters;
         bool ext_ifencei;
         bool ext_icsr;
+        bool ext_svinval;
         bool ext_svnapot;
         bool ext_svpbmt;
         bool ext_zfh;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5bbedc254c..1d3ff1efe1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -809,3 +809,10 @@ fcvt_l_h   1100010  00010 ..... ... ..... 1010011 @r2_rm
 fcvt_lu_h  1100010  00011 ..... ... ..... 1010011 @r2_rm
 fcvt_h_l   1101010  00010 ..... ... ..... 1010011 @r2_rm
 fcvt_h_lu  1101010  00011 ..... ... ..... 1010011 @r2_rm
+
+# *** Svinval Standard Extension ***
+sinval_vma        0001011 ..... ..... 000 00000 1110011 @sfence_vma
+sfence_w_inval    0001100 00000 00000 000 00000 1110011
+sfence_inval_ir   0001100 00001 00000 000 00000 1110011
+hinval_vvma       0010011 ..... ..... 000 00000 1110011 @hfence_vvma
+hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
new file mode 100644
index 0000000000..1dde665661
--- /dev/null
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -0,0 +1,75 @@
+/*
+ * RISC-V translation routines for the Svinval Standard Instruction Set.
+ *
+ * Copyright (c) 2020-2021 PLCT lab
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_SVINVAL(ctx) do {                    \
+    if (!RISCV_CPU(ctx->cs)->cfg.ext_svinval) {      \
+        return false;                                \
+    }                                                \
+} while (0)
+
+static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    /* Do the same as sfence.vma currently */
+    REQUIRE_EXT(ctx, RVS);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_tlb_flush(cpu_env);
+    return true;
+#endif
+    return false;
+}
+
+static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    REQUIRE_EXT(ctx, RVS);
+    /* Do nothing currently */
+    return true;
+}
+
+static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    REQUIRE_EXT(ctx, RVS);
+    /* Do nothing currently */
+    return true;
+}
+
+static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    /* Do the same as hfence.vvma currently */
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_hyp_tlb_flush(cpu_env);
+    return true;
+#endif
+    return false;
+}
+
+static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
+{
+    REQUIRE_SVINVAL(ctx);
+    /* Do the same as hfence.gvma currently */
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    gen_helper_hyp_gvma_tlb_flush(cpu_env);
+    return true;
+#endif
+    return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0bbe80875..cbf3b43348 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -855,6 +855,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvb.c.inc"
 #include "insn_trans/trans_rvzfh.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_svinval.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
 #include "decode-insn16.c.inc"
-- 
2.17.1

[PATCH v6 5/5] target/riscv: add support for svpbmt extension

[Weiwei Li]

- add PTE_PBMT bits: It uses two PTE bits, but otherwise has no effect on QEMU, since QEMU is sequentially consistent and doesn't model PMAs currently
- add PTE_PBMT bit check for inner PTE

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
 target/riscv/cpu.c        | 1 +
 target/riscv/cpu_bits.h   | 2 ++
 target/riscv/cpu_helper.c | 4 +++-
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4efdc16780..44c8229d3a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -731,6 +731,7 @@ static Property riscv_cpu_properties[] = {
 
     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
+    DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
 
     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 41190ce985..e3d0425f7f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -489,7 +489,9 @@ typedef enum {
 #define PTE_A               0x040 /* Accessed */
 #define PTE_D               0x080 /* Dirty */
 #define PTE_SOFT            0x300 /* Reserved for Software */
+#define PTE_PBMT            0x6000000000000000 /* Page-based memory types */
 #define PTE_N               0x8000000000000000 /* NAPOT translation */
+#define PTE_ATTR            (PTE_N | PTE_PBMT) /* All attributes bits */
 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ef7d9b07bd..22ac2504ff 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -639,9 +639,11 @@ restart:
         if (!(pte & PTE_V)) {
             /* Invalid PTE */
             return TRANSLATE_FAIL;
+        } else if (!cpu->cfg.ext_svpbmt && (pte & (target_ulong)PTE_PBMT)) {
+            return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
-            if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_N)) {
+            if (pte & (target_ulong)(PTE_D | PTE_A | PTE_U | PTE_ATTR)) {
                 return TRANSLATE_FAIL;
             }
             base = ppn << PGSHIFT;
-- 
2.17.1

Re: [PATCH v6 0/5] support subsets of virtual memory extension

[Guo Ren]

On Tue, Jan 25, 2022 at 3:33 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset implements virtual memory related RISC-V extensions: Svnapot version 1.0, Svinval vesion 1.0, Svpbmt version 1.0.
>
> Specification:
> https://github.com/riscv/virtual-memory/tree/main/specs
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-virtmem-upstream-v6
>
> To test this implementation, specify cpu argument with 'svinval=true,svnapot=true,svpbmt=true'.
>
> This implementation can pass the riscv-tests for rv64ssvnapot.
>
> v6:
> * select ppn mask base on sxl
>
> v5:
> * merge patch https://lore.kernel.org/qemu-devel/1569456861-8502-1-git-send-email-guoren@kernel.org/
> * relax pte attribute check
>
> v4:
> * fix encodings for hinval_vvma and hinval_gvma
> * partition inner PTE check into several steps
> * improve commit messages to describe changes
>
> v3:
> * drop "x-" in exposed properties
>
> v2:
> * add extension check for svnapot and svpbmt
>
> Guo Ren (1):
>   target/riscv: Ignore reserved bits in PTE for RV64
>
> Weiwei Li (4):
>   target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
>   target/riscv: add support for svnapot extension
>   target/riscv: add support for svinval extension
>   target/riscv: add support for svpbmt extension
>
>  target/riscv/cpu.c                          |  4 ++
>  target/riscv/cpu.h                          | 14 ++++
>  target/riscv/cpu_bits.h                     | 10 +++
>  target/riscv/cpu_helper.c                   | 34 +++++++++-
>  target/riscv/insn32.decode                  |  7 ++
>  target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++
>  target/riscv/translate.c                    |  1 +
>  7 files changed, 142 insertions(+), 3 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc
>
> --
> 2.17.1
>
>

Tested-by: Guo Ren <guoren@kernel.org>

-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/