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From: Fabiano Rosas <farosas@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, danielhb413@gmail.com,
	qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au
Subject: [PATCH 4/8] target/ppc: 74xx: External interrupt cleanup
Date: Wed, 26 Jan 2022 13:41:56 -0300	[thread overview]
Message-ID: <20220126164200.1048677-5-farosas@linux.ibm.com> (raw)
In-Reply-To: <20220126164200.1048677-1-farosas@linux.ibm.com>

The 74xx don't have MSR_HV so all the LPES0 logic can be removed.

Also remove the BookE IRQ code.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 38 --------------------------------------
 1 file changed, 38 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0d8c66b98f..b9a1d7ae7e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -555,7 +555,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
 {
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
-    int excp_model = env->excp_model;
     target_ulong msr, new_msr, vector;
     int srr0, srr1, lev = -1;
 
@@ -625,44 +624,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
         msr |= env->error_code;
         break;
     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
-    {
-        bool lpes0;
-
-        cs = CPU(cpu);
-
-        /*
-         * Exception targeting modifiers
-         *
-         * LPES0 is supported on POWER7/8/9
-         * LPES1 is not supported (old iSeries mode)
-         *
-         * On anything else, we behave as if LPES0 is 1
-         * (externals don't alter MSR:HV)
-         */
-#if defined(TARGET_PPC64)
-        if (excp_model == POWERPC_EXCP_POWER7 ||
-            excp_model == POWERPC_EXCP_POWER8 ||
-            excp_model == POWERPC_EXCP_POWER9 ||
-            excp_model == POWERPC_EXCP_POWER10) {
-            lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
-        } else
-#endif /* defined(TARGET_PPC64) */
-        {
-            lpes0 = true;
-        }
-
-        if (!lpes0) {
-            new_msr |= (target_ulong)MSR_HVB;
-            new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-            srr0 = SPR_HSRR0;
-            srr1 = SPR_HSRR1;
-        }
-        if (env->mpic_proxy) {
-            /* IACK the IRQ on delivery */
-            env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
-        }
         break;
-    }
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
         /* Get rS/rD and rA from faulting opcode */
         /*
-- 
2.34.1



  parent reply	other threads:[~2022-01-26 16:52 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-26 16:41 [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) Fabiano Rosas
2022-01-26 16:41 ` [PATCH 1/8] target/ppc: Introduce powerpc_excp_74xx Fabiano Rosas
2022-01-26 16:41 ` [PATCH 2/8] target/ppc: Simplify powerpc_excp_74xx Fabiano Rosas
2022-01-26 16:41 ` [PATCH 3/8] target/ppc: 74xx: Machine Check exception cleanup Fabiano Rosas
2022-01-26 16:41 ` Fabiano Rosas [this message]
2022-01-26 16:41 ` [PATCH 5/8] target/ppc: 74xx: Program " Fabiano Rosas
2022-01-26 16:41 ` [PATCH 6/8] target/ppc: 74xx: System Call " Fabiano Rosas
2022-01-26 16:41 ` [PATCH 7/8] target/ppc: 74xx: System Reset interrupt cleanup Fabiano Rosas
2022-01-26 16:42 ` [PATCH 8/8] target/ppc: 74xx: Set SRRs directly in exception code Fabiano Rosas
2022-01-26 17:55 ` [PATCH 0/8] target/ppc: powerpc_excp improvements [74xx] (5/n) BALATON Zoltan
2022-01-26 18:23   ` Cédric Le Goater
2022-01-26 20:00     ` BALATON Zoltan
2022-01-26 21:58   ` Fabiano Rosas
2022-01-27 14:40 ` Mark Cave-Ayland
2022-01-27 15:16   ` Fabiano Rosas
2022-01-27 16:51     ` Cédric Le Goater

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