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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 18:24:09.6735 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b41d9c19-8d71-464c-9c7f-08d9e1c2361e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0040.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6712 Received-SPF: pass client-ip=40.107.223.69; envelope-from=figlesia@xilinx.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, luc@lmichel.fr, frasse.iglesias@gmail.com, alistair@alistair23.me, qemu-devel@nongnu.org, alistair23@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jan 27, 2022 at 05:27:55PM +0000, Peter Maydell wrote: > On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias > wrote: > > > > Hi, > > > > This series attempts to add support for Xilinx Versal's PMC SLCR > > (system-level control registers) and OSPI flash memory controller to > > Xilinx Versal virt machine. > > > > The series start with adding a model of Versal's PMC SLCR and connecting > > the model to the Versal virt machine. The series then adds a couple of > > headers into the xlnx_csu_dma.h needed for building and reusing it later > > with the OSPI. The series thereafter introduces a DMA control interface > > and implements the interface in the xlnx_csu_dma for being able to reuse > > and control the DMA with the OSPI controller. Thereafter a model of > > Versal's OSPI controller is added and connected to the Versal virt > > machine. The series then ends with adding initial support for the Micron > > Xccelera mt35xu01g flash and flashes of this type are connected to the > > OSPI in the Versal virt machine. > > Hi Peter, > Applied to target-arm.next, thanks. (I fixed the indent issue > Luc noticed in patch 6.) Thanks a lot for above Peter! :) Also, thank you everybody for taking the time to review and providing me great feedback! Best regards, Francisco Iglesias > > -- PMM