From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>,
lazyparser@gmail.com, ardxwe@gmail.com
Subject: [PATCH v5 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
Date: Fri, 28 Jan 2022 21:16:43 +0800 [thread overview]
Message-ID: <20220128131643.13938-7-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220128131643.13938-1-liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7006e6647b..e96d0a73f5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -746,6 +746,11 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false),
+ DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false),
+ DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false),
+ DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
+
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
--
2.17.1
prev parent reply other threads:[~2022-01-28 14:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-28 13:16 [PATCH v5 0/6] support subsets of Float-Point in Integer Registers extensions Weiwei Li
2022-01-28 13:16 ` [PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Weiwei Li
2022-01-28 13:16 ` [PATCH v5 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx Weiwei Li
2022-01-28 13:16 ` [PATCH v5 3/6] target/riscv: add support for zfinx Weiwei Li
2022-01-28 13:16 ` [PATCH v5 4/6] target/riscv: add support for zdinx Weiwei Li
2022-01-28 13:16 ` [PATCH v5 5/6] target/riscv: add support for zhinx/zhinxmin Weiwei Li
2022-01-28 13:16 ` Weiwei Li [this message]
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