From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>,
"Fabiano Rosas" <farosas@linux.ibm.com>
Subject: [PULL 29/41] target/ppc: Simplify powerpc_excp_books
Date: Mon, 31 Jan 2022 12:07:59 +0100 [thread overview]
Message-ID: <20220131110811.619053-30-clg@kaod.org> (raw)
In-Reply-To: <20220131110811.619053-1-clg@kaod.org>
From: Fabiano Rosas <farosas@linux.ibm.com>
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- Always uses HV_EMU if the CPU has MSR_HV;
- Exceptions always delivered in 64 bit.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSEG
POWERPC_EXCP_DSI
POWERPC_EXCP_EXTERNAL
POWERPC_EXCP_FPU
POWERPC_EXCP_FU
POWERPC_EXCP_HDECR
POWERPC_EXCP_HDSI
POWERPC_EXCP_HISI
POWERPC_EXCP_HVIRT
POWERPC_EXCP_HV_EMU
POWERPC_EXCP_HV_FU
POWERPC_EXCP_ISEG
POWERPC_EXCP_ISI
POWERPC_EXCP_MAINT
POWERPC_EXCP_MCHECK
POWERPC_EXCP_PERFM
POWERPC_EXCP_PROGRAM
POWERPC_EXCP_RESET
POWERPC_EXCP_SDOOR_HV
POWERPC_EXCP_SYSCALL
POWERPC_EXCP_SYSCALL_VECTORED
POWERPC_EXCP_THERM
POWERPC_EXCP_TRACE
POWERPC_EXCP_VPU
POWERPC_EXCP_VPUA
POWERPC_EXCP_VSXU
POWERPC_EXCP_HV_MAINT
POWERPC_EXCP_SDOOR
(I added the two above that were not being considered. They used to be
"Invalid exception". Now they become "Unimplemented exception" which
is more accurate.)
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220124184605.999353-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 161 ++++-----------------------------------
1 file changed, 14 insertions(+), 147 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a2a605f8f59e..161b207bc7b8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -551,6 +551,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+#ifdef TARGET_PPC64
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
@@ -568,11 +569,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
excp, env->error_code);
/* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
+ msr = env->msr & ~0x783f0000ULL;
/*
* new interrupt handler msr preserves existing HV and ME unless
@@ -593,29 +590,13 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
}
/*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
+ * We don't want to generate a Hypervisor Emulation Assistance
+ * Interrupt if we don't have HVB in msr_mask (PAPR mode).
*/
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
+ if (excp == POWERPC_EXCP_HV_EMU && !(env->msr_mask & MSR_HVB)) {
excp = POWERPC_EXCP_PROGRAM;
}
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
cpu_abort(cs, "Raised an exception without defined vector %d\n",
@@ -625,22 +606,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
vector |= env->excp_prefix;
switch (excp) {
- case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_G2:
- break;
- default:
- goto excp_invalid;
- }
- break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
if (msr_me == 0) {
/*
@@ -817,50 +782,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
env->ctr = msr;
break;
case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
- break;
- case POWERPC_EXCP_DTLB: /* Data TLB error */
- case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
if (msr_pow) {
@@ -890,8 +813,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
/* fall through */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
case POWERPC_EXCP_HV_EMU:
case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
@@ -903,70 +824,25 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
break;
case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
- case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_602:
- case POWERPC_EXCP_603:
- case POWERPC_EXCP_G2:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7x5:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_IO: /* IO error exception */
- case POWERPC_EXCP_RUNM: /* Run mode exception */
- case POWERPC_EXCP_EMUL: /* Emulation trap exception */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
- case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
- case POWERPC_EXCP_SMI: /* System management interrupt */
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
+ case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */
+ case POWERPC_EXCP_HV_MAINT: /* Hypervisor Maintenance exception */
cpu_abort(cs, "%s exception not implemented\n",
powerpc_excp_name(excp));
break;
default:
- excp_invalid:
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
}
@@ -991,22 +867,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)1 << MSR_LE;
}
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
+ new_msr |= (target_ulong)1 << MSR_SF;
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
/* Save PC */
@@ -1021,6 +882,12 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+#else
+static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
+{
+ g_assert_not_reached();
+}
+#endif
/*
* Note that this function should be greatly optimized when called
--
2.34.1
next prev parent reply other threads:[~2022-01-31 11:48 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-31 11:07 [PULL 00/41] ppc queue Cédric Le Goater
2022-01-31 11:07 ` [PULL 01/41] spapr: Force 32bit when resetting a core Cédric Le Goater
2022-01-31 11:07 ` [PULL 02/41] target/ppc: 603: fix restore of GPRs 0-3 on rfi Cédric Le Goater
2022-01-31 12:01 ` Mark Cave-Ayland
2022-01-31 14:11 ` Cédric Le Goater
2022-01-31 16:59 ` Mark Cave-Ayland
2022-01-31 17:04 ` Peter Maydell
2022-01-31 19:00 ` Mark Cave-Ayland
2022-01-31 17:50 ` Cédric Le Goater
2022-01-31 19:08 ` Mark Cave-Ayland
2022-02-01 8:01 ` Cédric Le Goater
2022-01-31 11:07 ` [PULL 03/41] target/ppc/mmu_common: Fix SRR1/MSR error code on Book-E Cédric Le Goater
2022-01-31 11:07 ` [PULL 04/41] ppc/pnv: Fail DMA access if page permissions are not correct Cédric Le Goater
2022-01-31 11:07 ` [PULL 05/41] ppc/pnv: use a do-while() loop in pnv_phb3_translate_tve() Cédric Le Goater
2022-01-31 11:07 ` [PULL 06/41] ppc/pnv: use a do-while() loop in pnv_phb4_translate_tve() Cédric Le Goater
2022-01-31 11:07 ` [PULL 07/41] ppc/xive: check return value of ldq_be_dma() Cédric Le Goater
2022-01-31 11:07 ` [PULL 08/41] target/ppc: fix 'skip KVM' cond in cpu_interrupt_exittb() Cédric Le Goater
2022-01-31 11:07 ` [PULL 09/41] spapr.c: check bus != NULL in spapr_get_fw_dev_path() Cédric Le Goater
2022-01-31 11:07 ` [PULL 10/41] target/ppc: Fix test on mmu_model in hreg_compute_hflags_value() Cédric Le Goater
2022-01-31 11:07 ` [PULL 11/41] target/ppc: Put do_rfi under a TCG-only block Cédric Le Goater
2022-01-31 11:07 ` [PULL 12/41] hw/ppc/vof: Add missing includes Cédric Le Goater
2022-01-31 11:07 ` [PULL 13/41] ppc/ppc405: Fix TLB flushing Cédric Le Goater
2022-01-31 11:07 ` [PULL 14/41] target/ppc: 405: Rename MSR_POW to MSR_WE Cédric Le Goater
2022-01-31 11:07 ` [PULL 15/41] target/ppc: 405: Add missing MSR_ME bit Cédric Le Goater
2022-01-31 11:07 ` [PULL 16/41] target/ppc: Introduce powerpc_excp_40x Cédric Le Goater
2022-01-31 11:07 ` [PULL 17/41] target/ppc: Simplify powerpc_excp_40x Cédric Le Goater
2022-01-31 11:07 ` [PULL 18/41] target/ppc: 405: Critical exceptions cleanup Cédric Le Goater
2022-01-31 11:07 ` [PULL 19/41] target/ppc: 405: Machine check exception cleanup Cédric Le Goater
2022-01-31 11:07 ` [PULL 20/41] target/ppc: 405: External " Cédric Le Goater
2022-01-31 11:07 ` [PULL 21/41] target/ppc: 405: System call " Cédric Le Goater
2022-01-31 11:07 ` [PULL 22/41] target/ppc: 405: Alignment " Cédric Le Goater
2022-01-31 11:07 ` [PULL 23/41] target/ppc: 405: Debug " Cédric Le Goater
2022-01-31 11:07 ` [PULL 24/41] target/ppc: 405: Data Storage " Cédric Le Goater
2022-01-31 11:07 ` [PULL 25/41] target/ppc: 405: Instruction storage interrupt cleanup Cédric Le Goater
2022-01-31 11:07 ` [PULL 26/41] target/ppc: 405: Program exception cleanup Cédric Le Goater
2022-01-31 11:07 ` [PULL 27/41] target/ppc: 405: Watchdog timer " Cédric Le Goater
2022-01-31 11:07 ` [PULL 28/41] target/ppc: Introduce powerpc_excp_books Cédric Le Goater
2022-01-31 11:07 ` Cédric Le Goater [this message]
2022-01-31 11:08 ` [PULL 30/41] target/ppc: books: Machine Check exception cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 31/41] target/ppc: books: External interrupt cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 32/41] target/ppc: books: Program exception cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 33/41] target/ppc: Introduce powerpc_excp_74xx Cédric Le Goater
2022-01-31 11:08 ` [PULL 34/41] target/ppc: Simplify powerpc_excp_74xx Cédric Le Goater
2022-01-31 11:08 ` [PULL 35/41] target/ppc: 74xx: Machine Check exception cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 36/41] target/ppc: 74xx: External interrupt cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 37/41] target/ppc: 74xx: Program exception cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 38/41] target/ppc: 74xx: System Call " Cédric Le Goater
2022-01-31 11:08 ` [PULL 39/41] target/ppc: 74xx: System Reset interrupt cleanup Cédric Le Goater
2022-01-31 11:08 ` [PULL 40/41] target/ppc: 74xx: Set SRRs directly in exception code Cédric Le Goater
2022-01-31 11:08 ` [PULL 41/41] target/ppc: Remove support for the PowerPC 602 CPU Cédric Le Goater
2022-01-31 19:02 ` [PULL 00/41] ppc queue Peter Maydell
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