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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
	luc@lmichel.fr, sai.pavan.boddu@xilinx.com,
	frasse.iglesias@gmail.com, alistair@alistair23.me,
	richard.henderson@linaro.org, qemu-devel@nongnu.org,
	francisco.iglesias@xilinx.com, frederic.konrad@adacore.com,
	qemu-arm@nongnu.org
Subject: Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control
Date: Mon, 31 Jan 2022 13:17:20 +0100	[thread overview]
Message-ID: <20220131121720.GS3586016@toto> (raw)
In-Reply-To: <24f93c21-33a6-091f-206f-b80f505b6ddb@amsat.org>

On Mon, Jan 31, 2022 at 12:35:54AM +0100, Philippe Mathieu-Daudé wrote:
> On 31/1/22 00:12, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > 
> > Add a model of the Xilinx ZynqMP APU Control.
> > 
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >   include/hw/misc/xlnx-zynqmp-apu-ctrl.h |  91 +++++++++
> >   hw/misc/xlnx-zynqmp-apu-ctrl.c         | 257 +++++++++++++++++++++++++
> >   hw/misc/meson.build                    |   1 +
> >   3 files changed, 349 insertions(+)
> >   create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> >   create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
> > 
> > diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > new file mode 100644
> > index 0000000000..44bf264cef
> > --- /dev/null
> > +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
> > @@ -0,0 +1,91 @@
> > +/*
> > + * QEMU model of ZynqMP APU Control.
> > + *
> > + * Copyright (c) 2013-2022 Xilinx Inc
> > + * SPDX-License-Identifier: GPL-2.0-or-later
> > + *
> > + * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
> > + * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + */
> > +
> > +#include "hw/sysbus.h"
> > +#include "hw/register.h"
> > +#include "target/arm/cpu.h"
> > +
> > +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
> > +
> > +#define XLNX_ZYNQMP_APU(obj) \
> > +     OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL)
> ...
> 
> > +#define APU_R_MAX ((R_PWRSTAT) + 1)
> > +
> > +#define NUM_CPUS 4
> 
> Hmm isn't it APU_MAX_CPU?
> 


Thanks Philippe. Yes, this was a little confusing. The values happen to be the
same but they belong to different models. For example, the apu-ctrl model will be
reused in Versal.

Anyways, for v2 I've renamed the macros to CRF_MAX_CPU and APU_MAX_CPU respectevly.
I hope that makes things clearer.

Thanks,
Edgar


  reply	other threads:[~2022-01-31 14:12 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-30 23:12 [PATCH v1 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 1/6] hw/arm/xlnx-zynqmp: Add unimplemented SERDES area Edgar E. Iglesias
2022-01-30 23:37   ` Philippe Mathieu-Daudé via
2022-01-31 15:21   ` Francisco Iglesias
2022-01-31 15:32   ` Peter Maydell
2022-01-31 17:30     ` Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 2/6] target/arm: Make rvbar settable after realize Edgar E. Iglesias
2022-02-03 20:21   ` Luc Michel
2022-01-30 23:12 ` [PATCH v1 3/6] hw/misc: Add a model of the Xilinx ZynqMP CRF Edgar E. Iglesias
2022-01-30 23:32   ` Philippe Mathieu-Daudé via
2022-01-31 15:35   ` Francisco Iglesias
2022-01-31 17:27     ` Edgar E. Iglesias
2022-01-31 17:51       ` Edgar E. Iglesias
2022-01-30 23:12 ` [PATCH v1 4/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:33   ` Philippe Mathieu-Daudé via
2022-01-31 15:37   ` Francisco Iglesias
2022-02-03 20:23   ` Luc Michel
2022-01-30 23:12 ` [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Edgar E. Iglesias
2022-01-30 23:35   ` Philippe Mathieu-Daudé via
2022-01-31 12:17     ` Edgar E. Iglesias [this message]
2022-01-31 23:21       ` Philippe Mathieu-Daudé via
2022-01-31 15:46   ` Francisco Iglesias
2022-01-30 23:12 ` [PATCH v1 6/6] hw/arm/xlnx-zynqmp: Connect the " Edgar E. Iglesias
2022-01-30 23:37   ` Philippe Mathieu-Daudé via
2022-01-31 15:48   ` Francisco Iglesias
2022-02-03 20:26   ` Luc Michel

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