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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id j2sm16165lfc.174.2022.01.31.04.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jan 2022 04:17:21 -0800 (PST) Date: Mon, 31 Jan 2022 13:17:20 +0100 From: "Edgar E. Iglesias" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Message-ID: <20220131121720.GS3586016@toto> References: <20220130231206.34035-1-edgar.iglesias@gmail.com> <20220130231206.34035-6-edgar.iglesias@gmail.com> <24f93c21-33a6-091f-206f-b80f505b6ddb@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <24f93c21-33a6-091f-206f-b80f505b6ddb@amsat.org> X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::233 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x233.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, qemu-devel@nongnu.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jan 31, 2022 at 12:35:54AM +0100, Philippe Mathieu-Daudé wrote: > On 31/1/22 00:12, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Add a model of the Xilinx ZynqMP APU Control. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++ > > hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++ > > hw/misc/meson.build | 1 + > > 3 files changed, 349 insertions(+) > > create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h > > create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c > > > > diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h > > new file mode 100644 > > index 0000000000..44bf264cef > > --- /dev/null > > +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h > > @@ -0,0 +1,91 @@ > > +/* > > + * QEMU model of ZynqMP APU Control. > > + * > > + * Copyright (c) 2013-2022 Xilinx Inc > > + * SPDX-License-Identifier: GPL-2.0-or-later > > + * > > + * Written by Peter Crosthwaite and > > + * Edgar E. Iglesias > > + * > > + */ > > + > > +#include "hw/sysbus.h" > > +#include "hw/register.h" > > +#include "target/arm/cpu.h" > > + > > +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" > > + > > +#define XLNX_ZYNQMP_APU(obj) \ > > + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL) > ... > > > +#define APU_R_MAX ((R_PWRSTAT) + 1) > > + > > +#define NUM_CPUS 4 > > Hmm isn't it APU_MAX_CPU? > Thanks Philippe. Yes, this was a little confusing. The values happen to be the same but they belong to different models. For example, the apu-ctrl model will be reused in Versal. Anyways, for v2 I've renamed the macros to CRF_MAX_CPU and APU_MAX_CPU respectevly. I hope that makes things clearer. Thanks, Edgar