* [PATCH] target/riscv: Fix vill field write in vtype
@ 2022-02-01 6:46 LIU Zhiwei
2022-02-02 0:38 ` Richard Henderson
2022-02-02 6:38 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: LIU Zhiwei @ 2022-02-01 6:46 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis, LIU Zhiwei
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 020d2e841f..3bd4aac9c9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -71,6 +71,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
env->vl = vl;
env->vtype = s2;
env->vstart = 0;
+ env->vill = 0;
return vl;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: Fix vill field write in vtype
2022-02-01 6:46 [PATCH] target/riscv: Fix vill field write in vtype LIU Zhiwei
@ 2022-02-02 0:38 ` Richard Henderson
2022-02-02 6:38 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2022-02-02 0:38 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv; +Cc: Alistair.Francis, bin.meng, palmer
On 2/1/22 17:46, LIU Zhiwei wrote:
> The guest should be able to set the vill bit as part of vsetvl.
>
> Currently we may set env->vill to 1 in the vsetvl helper, but there
> is nowhere that we set it to 0, so once it transitions to 1 it's stuck
> there until the system is reset.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
> target/riscv/vector_helper.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Fix vill field write in vtype
2022-02-01 6:46 [PATCH] target/riscv: Fix vill field write in vtype LIU Zhiwei
2022-02-02 0:38 ` Richard Henderson
@ 2022-02-02 6:38 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-02-02 6:38 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Tue, Feb 1, 2022 at 5:08 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> The guest should be able to set the vill bit as part of vsetvl.
>
> Currently we may set env->vill to 1 in the vsetvl helper, but there
> is nowhere that we set it to 0, so once it transitions to 1 it's stuck
> there until the system is reset.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 020d2e841f..3bd4aac9c9 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -71,6 +71,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
> env->vl = vl;
> env->vtype = s2;
> env->vstart = 0;
> + env->vill = 0;
> return vl;
> }
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-02-02 0:38 ` Richard Henderson
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