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Tsirkin" To: Peter Maydell Subject: Re: [PATCH v5 03/18] pci: isolated address space for PCI bus Message-ID: <20220202050526-mutt-send-email-mst@kernel.org> References: <20220126161120-mutt-send-email-mst@kernel.org> <20220127142253.21ab0025.alex.williamson@redhat.com> <20220131091623.6739464e.alex.williamson@redhat.com> <20220201082437.7dd940eb.alex.williamson@redhat.com> <9BD98DD7-CC28-49E1-8150-BDECF0324FFA@oracle.com> <20220201154736.576e2a7e.alex.williamson@redhat.com> MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.086, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "eduardo@habkost.net" , Elena Ufimtseva , Jag Raman , Beraldo Leal , "john.levon@nutanix.com" , John Johnson , "quintela@redhat.com" , qemu-devel , "armbru@redhat.com" , Alex Williamson , "thanos.makatos@nutanix.com" , =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Stefan Hajnoczi , Paolo Bonzini , Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , Eric Blake , "Dr. David Alan Gilbert" , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Feb 02, 2022 at 09:30:42AM +0000, Peter Maydell wrote: > > I/O port space is always the identity mapped CPU address space unless > > sparse translations are used to create multiple I/O port spaces (not > > implemented). I/O port space is only accessed by the CPU, there are no > > device initiated I/O port transactions, so the address space relative > > to the device is irrelevant. > > Does the PCI spec actually forbid any master except the CPU from > issuing I/O port transactions, or is it just that in practice nobody > makes a PCI device that does weird stuff like that ? > > thanks > -- PMM Hmm, the only thing vaguely related in the spec that I know of is this: PCI Express supports I/O Space for compatibility with legacy devices which require their use. Future revisions of this specification may deprecate the use of I/O Space. Alex, what did you refer to? -- MST