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Wed, 02 Feb 2022 09:12:30 -0800 (PST) Received: from redhat.com ([38.15.36.239]) by smtp.gmail.com with ESMTPSA id p82sm10655207oib.25.2022.02.02.09.12.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Feb 2022 09:12:30 -0800 (PST) Date: Wed, 2 Feb 2022 10:12:28 -0700 From: Alex Williamson To: Peter Maydell Subject: Re: [PATCH v5 03/18] pci: isolated address space for PCI bus Message-ID: <20220202101228.54b7e46c.alex.williamson@redhat.com> In-Reply-To: References: <1CACFB08-1BBC-4ECC-9C0B-6F377018D795@oracle.com> <20220126161120-mutt-send-email-mst@kernel.org> <20220127142253.21ab0025.alex.williamson@redhat.com> <20220131091623.6739464e.alex.williamson@redhat.com> <20220201082437.7dd940eb.alex.williamson@redhat.com> <9BD98DD7-CC28-49E1-8150-BDECF0324FFA@oracle.com> <20220201154736.576e2a7e.alex.williamson@redhat.com> X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.33; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=alex.williamson@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.086, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "eduardo@habkost.net" , Elena Ufimtseva , Jag Raman , Beraldo Leal , "john.levon@nutanix.com" , John Johnson , "Michael S. Tsirkin" , qemu-devel , "armbru@redhat.com" , "quintela@redhat.com" , "thanos.makatos@nutanix.com" , =?UTF-8?B?TWFyYy1BbmRyw6k=?= Lureau , Stefan Hajnoczi , Paolo Bonzini , "Daniel P. =?UTF-8?B?QmVycmFuZ8Op?=" , Eric Blake , "Dr. David Alan Gilbert" , Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 2 Feb 2022 09:30:42 +0000 Peter Maydell wrote: > On Tue, 1 Feb 2022 at 23:51, Alex Williamson wrote: > > > > On Tue, 1 Feb 2022 21:24:08 +0000 > > Jag Raman wrote: > > > The PCIBus data structure already has address_space_mem and > > > address_space_io to contain the BAR regions of devices attached > > > to it. I understand that these two PCIBus members form the > > > PCI address space. > > > > These are the CPU address spaces. When there's no IOMMU, the PCI bus is > > identity mapped to the CPU address space. When there is an IOMMU, the > > device address space is determined by the granularity of the IOMMU and > > may be entirely separate from address_space_mem. > > Note that those fields in PCIBus are just whatever MemoryRegions > the pci controller model passed in to the call to pci_root_bus_init() > or equivalent. They may or may not be specifically the CPU's view > of anything. (For instance on the versatilepb board, the PCI controller > is visible to the CPU via several MMIO "windows" at known addresses, > which let the CPU access into the PCI address space at a programmable > offset. We model that by creating a couple of container MRs which > we pass to pci_root_bus_init() to be the PCI memory and IO spaces, > and then using alias MRs to provide the view into those at the > guest-programmed offset. The CPU sees those windows, and doesn't > have direct access to the whole PCIBus::address_space_mem.) > I guess you could say they're the PCI controller's view of the PCI > address space ? Sure, that's fair. > We have a tendency to be a bit sloppy with use of AddressSpaces > within QEMU where it happens that the view of the world that a > DMA-capable device matches that of the CPU, but conceptually > they can definitely be different, especially in the non-x86 world. > (Linux also confuses matters here by preferring to program a 1:1 > mapping even if the hardware is more flexible and can do other things. > The model of the h/w in QEMU should support the other cases too, not > just 1:1.) Right, this is why I prefer to look at the device address space as simply an IOVA. The IOVA might be a direct physical address or coincidental identity mapped physical address via an IOMMU, but none of that should be the concern of the device. > > I/O port space is always the identity mapped CPU address space unless > > sparse translations are used to create multiple I/O port spaces (not > > implemented). I/O port space is only accessed by the CPU, there are no > > device initiated I/O port transactions, so the address space relative > > to the device is irrelevant. > > Does the PCI spec actually forbid any master except the CPU from > issuing I/O port transactions, or is it just that in practice nobody > makes a PCI device that does weird stuff like that ? As realized in reply to MST, more the latter. Not used, no point to enabling, no means to enable depending on the physical IOMMU implementation. Thanks, Alex