* [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy
2022-02-07 18:30 [PATCH 0/4] target/ppc: powerpc_excp improvements (9/9) Fabiano Rosas
@ 2022-02-07 18:30 ` Fabiano Rosas
2022-02-08 2:28 ` David Gibson
2022-02-08 9:11 ` Cédric Le Goater
2022-02-07 18:30 ` [PATCH 2/4] target/ppc: powerpc_excp: Move common code to the caller function Fabiano Rosas
` (2 subsequent siblings)
3 siblings, 2 replies; 8+ messages in thread
From: Fabiano Rosas @ 2022-02-07 18:30 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Now that all CPU families have their own separate exception
dispatching code we can remove powerpc_excp_legacy.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 477 +--------------------------------------
1 file changed, 3 insertions(+), 474 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 0050c8447f..c6646503aa 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -163,7 +163,7 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
env->error_code);
}
-
+#if defined(TARGET_PPC64)
static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
target_ulong *msr)
{
@@ -267,7 +267,6 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
target_ulong *new_msr,
target_ulong *vector)
{
-#if defined(TARGET_PPC64)
CPUPPCState *env = &cpu->env;
bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1);
bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB);
@@ -356,8 +355,8 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
*vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */
}
}
-#endif
}
+#endif
static void powerpc_set_excp_state(PowerPCCPU *cpu,
target_ulong vector, target_ulong msr)
@@ -1641,476 +1640,6 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
}
#endif
-/*
- * Note that this function should be greatly optimized when called
- * with a constant excp, from ppc_hw_interrupt
- */
-static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
-{
- CPUState *cs = CPU(cpu);
- CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
- target_ulong msr, new_msr, vector;
- int srr0, srr1, lev = -1;
-
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
- /* new srr1 value excluding must-be-zero bits */
- if (excp_model == POWERPC_EXCP_BOOKE) {
- msr = env->msr;
- } else {
- msr = env->msr & ~0x783f0000ULL;
- }
-
- /*
- * new interrupt handler msr preserves existing HV and ME unless
- * explicitly overriden
- */
- new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
-
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
- /*
- * check for special resume at 0x100 from doze/nap/sleep/winkle on
- * P7/P8/P9
- */
- if (env->resume_as_sreset) {
- excp = powerpc_reset_wakeup(cs, env, excp, &msr);
- }
-
- /*
- * Hypervisor emulation assistance interrupt only exists on server
- * arch 2.05 server or later. We also don't want to generate it if
- * we don't have HVB in msr_mask (PAPR mode).
- */
- if (excp == POWERPC_EXCP_HV_EMU
-#if defined(TARGET_PPC64)
- && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
-#endif /* defined(TARGET_PPC64) */
-
- ) {
- excp = POWERPC_EXCP_PROGRAM;
- }
-
-#ifdef TARGET_PPC64
- /*
- * SPEU and VPU share the same IVOR but they exist in different
- * processors. SPEU is e500v1/2 only and VPU is e6500 only.
- */
- if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
- excp = POWERPC_EXCP_SPEU;
- }
-#endif
-
- vector = env->excp_vectors[excp];
- if (vector == (target_ulong)-1ULL) {
- cpu_abort(cs, "Raised an exception without defined vector %d\n",
- excp);
- }
-
- vector |= env->excp_prefix;
-
- switch (excp) {
- case POWERPC_EXCP_CRITICAL: /* Critical input */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_6xx:
- break;
- default:
- goto excp_invalid;
- }
- break;
- case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
- /*
- * Machine check exception is not enabled. Enter
- * checkstop state.
- */
- fprintf(stderr, "Machine check while not allowed. "
- "Entering checkstop state\n");
- if (qemu_log_separate()) {
- qemu_log("Machine check while not allowed. "
- "Entering checkstop state\n");
- }
- cs->halted = 1;
- cpu_interrupt_exittb(cs);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR).
- */
- new_msr |= (target_ulong)MSR_HVB;
- }
-
- /* machine check exceptions don't have ME set */
- new_msr &= ~((target_ulong)1 << MSR_ME);
-
- /* XXX: should also have something loaded in DAR / DSISR */
- switch (excp_model) {
- case POWERPC_EXCP_40x:
- srr0 = SPR_40x_SRR2;
- srr1 = SPR_40x_SRR3;
- break;
- case POWERPC_EXCP_BOOKE:
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_MCSRR0;
- srr1 = SPR_BOOKE_MCSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
- break;
- default:
- break;
- }
- break;
- case POWERPC_EXCP_DSI: /* Data storage exception */
- trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
- break;
- case POWERPC_EXCP_ISI: /* Instruction storage exception */
- trace_ppc_excp_isi(msr, env->nip);
- msr |= env->error_code;
- break;
- case POWERPC_EXCP_EXTERNAL: /* External input */
- {
- bool lpes0;
-
- cs = CPU(cpu);
-
- /*
- * Exception targeting modifiers
- *
- * LPES0 is supported on POWER7/8/9
- * LPES1 is not supported (old iSeries mode)
- *
- * On anything else, we behave as if LPES0 is 1
- * (externals don't alter MSR:HV)
- */
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_POWER7 ||
- excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9 ||
- excp_model == POWERPC_EXCP_POWER10) {
- lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
- } else
-#endif /* defined(TARGET_PPC64) */
- {
- lpes0 = true;
- }
-
- if (!lpes0) {
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- }
- if (env->mpic_proxy) {
- /* IACK the IRQ on delivery */
- env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
- }
- break;
- }
- case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
- /*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
- */
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
- break;
- case POWERPC_EXCP_PROGRAM: /* Program exception */
- switch (env->error_code & ~0xF) {
- case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
- trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- return;
- }
-
- /*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
- */
- msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
- break;
- case POWERPC_EXCP_INVAL:
- trace_ppc_excp_inval(env->nip);
- msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
- break;
- case POWERPC_EXCP_PRIV:
- msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
- break;
- case POWERPC_EXCP_TRAP:
- msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
- break;
- default:
- /* Should never occur */
- cpu_abort(cs, "Invalid program exception %d. Aborting\n",
- env->error_code);
- break;
- }
- break;
- case POWERPC_EXCP_SYSCALL: /* System call exception */
- lev = env->error_code;
-
- if ((lev == 1) && cpu->vhyp) {
- dump_hcall(env);
- } else {
- dump_syscall(env);
- }
-
- /*
- * We need to correct the NIP which in this case is supposed
- * to point to the next instruction
- */
- env->nip += 4;
-
- /* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
- PPCVirtualHypervisorClass *vhc =
- PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->hypercall(cpu->vhyp, cpu);
- return;
- }
- if (lev == 1) {
- new_msr |= (target_ulong)MSR_HVB;
- }
- break;
- case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
- lev = env->error_code;
- dump_syscall(env);
- env->nip += 4;
- new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-
- vector += lev * 0x20;
-
- env->lr = env->nip;
- env->ctr = msr;
- break;
- case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
- case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
- case POWERPC_EXCP_DECR: /* Decrementer exception */
- break;
- case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- /* FIT on 4xx */
- trace_ppc_excp_print("FIT");
- break;
- case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- trace_ppc_excp_print("WDT");
- switch (excp_model) {
- case POWERPC_EXCP_BOOKE:
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- default:
- break;
- }
- break;
- case POWERPC_EXCP_DTLB: /* Data TLB error */
- case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- break;
- case POWERPC_EXCP_DEBUG: /* Debug interrupt */
- if (env->flags & POWERPC_FLAG_DE) {
- /* FIXME: choose one or the other based on CPU type */
- srr0 = SPR_BOOKE_DSRR0;
- srr1 = SPR_BOOKE_DSRR1;
-
- env->spr[SPR_BOOKE_CSRR0] = env->nip;
- env->spr[SPR_BOOKE_CSRR1] = msr;
-
- /* DBSR already modified by caller */
- } else {
- cpu_abort(cs, "Debug exception triggered on unsupported model\n");
- }
- break;
- case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
- env->spr[SPR_BOOKE_ESR] = ESR_SPV;
- break;
- case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- break;
- case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- srr0 = SPR_BOOKE_CSRR0;
- srr1 = SPR_BOOKE_CSRR1;
- break;
- case POWERPC_EXCP_RESET: /* System reset exception */
- /* A power-saving exception sets ME, otherwise it is unchanged */
- if (msr_pow) {
- /* indicate that we resumed from power save mode */
- msr |= 0x10000;
- new_msr |= ((target_ulong)1 << MSR_ME);
- }
- if (env->msr_mask & MSR_HVB) {
- /*
- * ISA specifies HV, but can be delivered to guest with HV
- * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
- */
- new_msr |= (target_ulong)MSR_HVB;
- } else {
- if (msr_pow) {
- cpu_abort(cs, "Trying to deliver power-saving system reset "
- "exception %d with no HV support\n", excp);
- }
- }
- break;
- case POWERPC_EXCP_DSEG: /* Data segment exception */
- case POWERPC_EXCP_ISEG: /* Instruction segment exception */
- case POWERPC_EXCP_TRACE: /* Trace exception */
- break;
- case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
- msr |= env->error_code;
- /* fall through */
- case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
- case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
- case POWERPC_EXCP_HV_EMU:
- case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
- break;
- case POWERPC_EXCP_VPU: /* Vector unavailable exception */
- case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
- case POWERPC_EXCP_FU: /* Facility unavailable exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
-#endif
- break;
- case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
-#ifdef TARGET_PPC64
- env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
-#endif
- break;
- case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
- trace_ppc_excp_print("PIT");
- break;
- case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- switch (excp_model) {
- case POWERPC_EXCP_6xx:
- /* Swap temporary saved registers with GPRs */
- if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
- new_msr |= (target_ulong)1 << MSR_TGPR;
- hreg_swap_gpr_tgpr(env);
- }
- /* fall through */
- case POWERPC_EXCP_7xx:
- ppc_excp_debug_sw_tlb(env, excp);
-
- msr |= env->crf[0] << 28;
- msr |= env->error_code; /* key, D/I, S/L bits */
- /* Set way using a LRU mechanism */
- msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
- break;
- default:
- cpu_abort(cs, "Invalid TLB miss exception\n");
- break;
- }
- break;
- case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
- case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
- case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- case POWERPC_EXCP_DABR: /* Data address breakpoint */
- case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
- case POWERPC_EXCP_SMI: /* System management interrupt */
- case POWERPC_EXCP_THERM: /* Thermal interrupt */
- case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
- case POWERPC_EXCP_VPUA: /* Vector assist exception */
- case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- case POWERPC_EXCP_MAINT: /* Maintenance exception */
- case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
- case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
- cpu_abort(cs, "%s exception not implemented\n",
- powerpc_excp_name(excp));
- break;
- default:
- excp_invalid:
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- break;
- }
-
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
- }
-
- /*
- * Sort out endianness of interrupt, this differs depending on the
- * CPU, the HV mode, etc...
- */
- if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
- new_msr |= (target_ulong)1 << MSR_LE;
- }
-
-#if defined(TARGET_PPC64)
- if (excp_model == POWERPC_EXCP_BOOKE) {
- if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
- /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
- new_msr |= (target_ulong)1 << MSR_CM;
- } else {
- vector = (uint32_t)vector;
- }
- } else {
- if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
- vector = (uint32_t)vector;
- } else {
- new_msr |= (target_ulong)1 << MSR_SF;
- }
- }
-#endif
-
- if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
- /* Save PC */
- env->spr[srr0] = env->nip;
-
- /* Save MSR */
- env->spr[srr1] = msr;
- }
-
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
-
- powerpc_set_excp_state(cpu, vector, new_msr);
-}
-
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
@@ -2139,7 +1668,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
powerpc_excp_books(cpu, excp);
break;
default:
- powerpc_excp_legacy(cpu, excp);
+ g_assert_not_reached();
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy
2022-02-07 18:30 ` [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy Fabiano Rosas
@ 2022-02-08 2:28 ` David Gibson
2022-02-08 9:11 ` Cédric Le Goater
1 sibling, 0 replies; 8+ messages in thread
From: David Gibson @ 2022-02-08 2:28 UTC (permalink / raw)
To: Fabiano Rosas; +Cc: danielhb413, qemu-ppc, qemu-devel, clg
[-- Attachment #1: Type: text/plain, Size: 21316 bytes --]
On Mon, Feb 07, 2022 at 03:30:33PM -0300, Fabiano Rosas wrote:
> Now that all CPU families have their own separate exception
> dispatching code we can remove powerpc_excp_legacy.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
> ---
> target/ppc/excp_helper.c | 477 +--------------------------------------
> 1 file changed, 3 insertions(+), 474 deletions(-)
Nice!
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 0050c8447f..c6646503aa 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -163,7 +163,7 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
> env->error_code);
> }
>
> -
> +#if defined(TARGET_PPC64)
> static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
> target_ulong *msr)
> {
> @@ -267,7 +267,6 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
> target_ulong *new_msr,
> target_ulong *vector)
> {
> -#if defined(TARGET_PPC64)
> CPUPPCState *env = &cpu->env;
> bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1);
> bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB);
> @@ -356,8 +355,8 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
> *vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */
> }
> }
> -#endif
> }
> +#endif
>
> static void powerpc_set_excp_state(PowerPCCPU *cpu,
> target_ulong vector, target_ulong msr)
> @@ -1641,476 +1640,6 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> }
> #endif
>
> -/*
> - * Note that this function should be greatly optimized when called
> - * with a constant excp, from ppc_hw_interrupt
> - */
> -static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
> -{
> - CPUState *cs = CPU(cpu);
> - CPUPPCState *env = &cpu->env;
> - int excp_model = env->excp_model;
> - target_ulong msr, new_msr, vector;
> - int srr0, srr1, lev = -1;
> -
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> - /* new srr1 value excluding must-be-zero bits */
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - msr = env->msr;
> - } else {
> - msr = env->msr & ~0x783f0000ULL;
> - }
> -
> - /*
> - * new interrupt handler msr preserves existing HV and ME unless
> - * explicitly overriden
> - */
> - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> -
> - /* target registers */
> - srr0 = SPR_SRR0;
> - srr1 = SPR_SRR1;
> -
> - /*
> - * check for special resume at 0x100 from doze/nap/sleep/winkle on
> - * P7/P8/P9
> - */
> - if (env->resume_as_sreset) {
> - excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> - }
> -
> - /*
> - * Hypervisor emulation assistance interrupt only exists on server
> - * arch 2.05 server or later. We also don't want to generate it if
> - * we don't have HVB in msr_mask (PAPR mode).
> - */
> - if (excp == POWERPC_EXCP_HV_EMU
> -#if defined(TARGET_PPC64)
> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> -#endif /* defined(TARGET_PPC64) */
> -
> - ) {
> - excp = POWERPC_EXCP_PROGRAM;
> - }
> -
> -#ifdef TARGET_PPC64
> - /*
> - * SPEU and VPU share the same IVOR but they exist in different
> - * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> - */
> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> - excp = POWERPC_EXCP_SPEU;
> - }
> -#endif
> -
> - vector = env->excp_vectors[excp];
> - if (vector == (target_ulong)-1ULL) {
> - cpu_abort(cs, "Raised an exception without defined vector %d\n",
> - excp);
> - }
> -
> - vector |= env->excp_prefix;
> -
> - switch (excp) {
> - case POWERPC_EXCP_CRITICAL: /* Critical input */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_6xx:
> - break;
> - default:
> - goto excp_invalid;
> - }
> - break;
> - case POWERPC_EXCP_MCHECK: /* Machine check exception */
> - if (msr_me == 0) {
> - /*
> - * Machine check exception is not enabled. Enter
> - * checkstop state.
> - */
> - fprintf(stderr, "Machine check while not allowed. "
> - "Entering checkstop state\n");
> - if (qemu_log_separate()) {
> - qemu_log("Machine check while not allowed. "
> - "Entering checkstop state\n");
> - }
> - cs->halted = 1;
> - cpu_interrupt_exittb(cs);
> - }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - }
> -
> - /* machine check exceptions don't have ME set */
> - new_msr &= ~((target_ulong)1 << MSR_ME);
> -
> - /* XXX: should also have something loaded in DAR / DSISR */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_MCSRR0;
> - srr1 = SPR_BOOKE_MCSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> - break;
> - default:
> - break;
> - }
> - break;
> - case POWERPC_EXCP_DSI: /* Data storage exception */
> - trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
> - break;
> - case POWERPC_EXCP_ISI: /* Instruction storage exception */
> - trace_ppc_excp_isi(msr, env->nip);
> - msr |= env->error_code;
> - break;
> - case POWERPC_EXCP_EXTERNAL: /* External input */
> - {
> - bool lpes0;
> -
> - cs = CPU(cpu);
> -
> - /*
> - * Exception targeting modifiers
> - *
> - * LPES0 is supported on POWER7/8/9
> - * LPES1 is not supported (old iSeries mode)
> - *
> - * On anything else, we behave as if LPES0 is 1
> - * (externals don't alter MSR:HV)
> - */
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_POWER7 ||
> - excp_model == POWERPC_EXCP_POWER8 ||
> - excp_model == POWERPC_EXCP_POWER9 ||
> - excp_model == POWERPC_EXCP_POWER10) {
> - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> - } else
> -#endif /* defined(TARGET_PPC64) */
> - {
> - lpes0 = true;
> - }
> -
> - if (!lpes0) {
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - }
> - if (env->mpic_proxy) {
> - /* IACK the IRQ on delivery */
> - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> - }
> - break;
> - }
> - case POWERPC_EXCP_ALIGN: /* Alignment exception */
> - /* Get rS/rD and rA from faulting opcode */
> - /*
> - * Note: the opcode fields will not be set properly for a
> - * direct store load/store, but nobody cares as nobody
> - * actually uses direct store segments.
> - */
> - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> - break;
> - case POWERPC_EXCP_PROGRAM: /* Program exception */
> - switch (env->error_code & ~0xF) {
> - case POWERPC_EXCP_FP:
> - if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
> - trace_ppc_excp_fp_ignore();
> - cs->exception_index = POWERPC_EXCP_NONE;
> - env->error_code = 0;
> - return;
> - }
> -
> - /*
> - * FP exceptions always have NIP pointing to the faulting
> - * instruction, so always use store_next and claim we are
> - * precise in the MSR.
> - */
> - msr |= 0x00100000;
> - env->spr[SPR_BOOKE_ESR] = ESR_FP;
> - break;
> - case POWERPC_EXCP_INVAL:
> - trace_ppc_excp_inval(env->nip);
> - msr |= 0x00080000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> - break;
> - case POWERPC_EXCP_PRIV:
> - msr |= 0x00040000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> - break;
> - case POWERPC_EXCP_TRAP:
> - msr |= 0x00020000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> - break;
> - default:
> - /* Should never occur */
> - cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> - env->error_code);
> - break;
> - }
> - break;
> - case POWERPC_EXCP_SYSCALL: /* System call exception */
> - lev = env->error_code;
> -
> - if ((lev == 1) && cpu->vhyp) {
> - dump_hcall(env);
> - } else {
> - dump_syscall(env);
> - }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> - /* "PAPR mode" built-in hypercall emulation */
> - if ((lev == 1) && cpu->vhyp) {
> - PPCVirtualHypervisorClass *vhc =
> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> - vhc->hypercall(cpu->vhyp, cpu);
> - return;
> - }
> - if (lev == 1) {
> - new_msr |= (target_ulong)MSR_HVB;
> - }
> - break;
> - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
> - lev = env->error_code;
> - dump_syscall(env);
> - env->nip += 4;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -
> - vector += lev * 0x20;
> -
> - env->lr = env->nip;
> - env->ctr = msr;
> - break;
> - case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> - case POWERPC_EXCP_DECR: /* Decrementer exception */
> - break;
> - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> - /* FIT on 4xx */
> - trace_ppc_excp_print("FIT");
> - break;
> - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> - trace_ppc_excp_print("WDT");
> - switch (excp_model) {
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - default:
> - break;
> - }
> - break;
> - case POWERPC_EXCP_DTLB: /* Data TLB error */
> - case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> - break;
> - case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> - if (env->flags & POWERPC_FLAG_DE) {
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_DSRR0;
> - srr1 = SPR_BOOKE_DSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> -
> - /* DBSR already modified by caller */
> - } else {
> - cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> - }
> - break;
> - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> - env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> - break;
> - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> - break;
> - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_RESET: /* System reset exception */
> - /* A power-saving exception sets ME, otherwise it is unchanged */
> - if (msr_pow) {
> - /* indicate that we resumed from power save mode */
> - msr |= 0x10000;
> - new_msr |= ((target_ulong)1 << MSR_ME);
> - }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - } else {
> - if (msr_pow) {
> - cpu_abort(cs, "Trying to deliver power-saving system reset "
> - "exception %d with no HV support\n", excp);
> - }
> - }
> - break;
> - case POWERPC_EXCP_DSEG: /* Data segment exception */
> - case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> - case POWERPC_EXCP_TRACE: /* Trace exception */
> - break;
> - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
> - msr |= env->error_code;
> - /* fall through */
> - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> - case POWERPC_EXCP_HV_EMU:
> - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - break;
> - case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> - case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> - case POWERPC_EXCP_FU: /* Facility unavailable exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> -#endif
> - break;
> - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -#endif
> - break;
> - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> - trace_ppc_excp_print("PIT");
> - break;
> - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> - case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> - case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> - switch (excp_model) {
> - case POWERPC_EXCP_6xx:
> - /* Swap temporary saved registers with GPRs */
> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> - new_msr |= (target_ulong)1 << MSR_TGPR;
> - hreg_swap_gpr_tgpr(env);
> - }
> - /* fall through */
> - case POWERPC_EXCP_7xx:
> - ppc_excp_debug_sw_tlb(env, excp);
> -
> - msr |= env->crf[0] << 28;
> - msr |= env->error_code; /* key, D/I, S/L bits */
> - /* Set way using a LRU mechanism */
> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> - break;
> - default:
> - cpu_abort(cs, "Invalid TLB miss exception\n");
> - break;
> - }
> - break;
> - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> - case POWERPC_EXCP_DABR: /* Data address breakpoint */
> - case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> - case POWERPC_EXCP_SMI: /* System management interrupt */
> - case POWERPC_EXCP_THERM: /* Thermal interrupt */
> - case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_VPUA: /* Vector assist exception */
> - case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> - case POWERPC_EXCP_MAINT: /* Maintenance exception */
> - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> - cpu_abort(cs, "%s exception not implemented\n",
> - powerpc_excp_name(excp));
> - break;
> - default:
> - excp_invalid:
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - break;
> - }
> -
> - /* Sanity check */
> - if (!(env->msr_mask & MSR_HVB)) {
> - if (new_msr & MSR_HVB) {
> - cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
> - "no HV support\n", excp);
> - }
> - if (srr0 == SPR_HSRR0) {
> - cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
> - "no HV support\n", excp);
> - }
> - }
> -
> - /*
> - * Sort out endianness of interrupt, this differs depending on the
> - * CPU, the HV mode, etc...
> - */
> - if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> - new_msr |= (target_ulong)1 << MSR_LE;
> - }
> -
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> - new_msr |= (target_ulong)1 << MSR_CM;
> - } else {
> - vector = (uint32_t)vector;
> - }
> - } else {
> - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> - vector = (uint32_t)vector;
> - } else {
> - new_msr |= (target_ulong)1 << MSR_SF;
> - }
> - }
> -#endif
> -
> - if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> - /* Save PC */
> - env->spr[srr0] = env->nip;
> -
> - /* Save MSR */
> - env->spr[srr1] = msr;
> - }
> -
> - /* This can update new_msr and vector if AIL applies */
> - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> -
> - powerpc_set_excp_state(cpu, vector, new_msr);
> -}
> -
> static void powerpc_excp(PowerPCCPU *cpu, int excp)
> {
> CPUPPCState *env = &cpu->env;
> @@ -2139,7 +1668,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
> powerpc_excp_books(cpu, excp);
> break;
> default:
> - powerpc_excp_legacy(cpu, excp);
> + g_assert_not_reached();
> }
> }
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy
2022-02-07 18:30 ` [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy Fabiano Rosas
2022-02-08 2:28 ` David Gibson
@ 2022-02-08 9:11 ` Cédric Le Goater
1 sibling, 0 replies; 8+ messages in thread
From: Cédric Le Goater @ 2022-02-08 9:11 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 2/7/22 19:30, Fabiano Rosas wrote:
> Now that all CPU families have their own separate exception
> dispatching code we can remove powerpc_excp_legacy.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Super :)
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 477 +--------------------------------------
> 1 file changed, 3 insertions(+), 474 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 0050c8447f..c6646503aa 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -163,7 +163,7 @@ static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
> env->error_code);
> }
>
> -
> +#if defined(TARGET_PPC64)
> static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
> target_ulong *msr)
> {
> @@ -267,7 +267,6 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
> target_ulong *new_msr,
> target_ulong *vector)
> {
> -#if defined(TARGET_PPC64)
> CPUPPCState *env = &cpu->env;
> bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1);
> bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB);
> @@ -356,8 +355,8 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
> *vector |= 0xc000000000003000ull; /* Apply scv's AIL=3 offset */
> }
> }
> -#endif
> }
> +#endif
>
> static void powerpc_set_excp_state(PowerPCCPU *cpu,
> target_ulong vector, target_ulong msr)
> @@ -1641,476 +1640,6 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> }
> #endif
>
> -/*
> - * Note that this function should be greatly optimized when called
> - * with a constant excp, from ppc_hw_interrupt
> - */
> -static inline void powerpc_excp_legacy(PowerPCCPU *cpu, int excp)
> -{
> - CPUState *cs = CPU(cpu);
> - CPUPPCState *env = &cpu->env;
> - int excp_model = env->excp_model;
> - target_ulong msr, new_msr, vector;
> - int srr0, srr1, lev = -1;
> -
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> - /* new srr1 value excluding must-be-zero bits */
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - msr = env->msr;
> - } else {
> - msr = env->msr & ~0x783f0000ULL;
> - }
> -
> - /*
> - * new interrupt handler msr preserves existing HV and ME unless
> - * explicitly overriden
> - */
> - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
> -
> - /* target registers */
> - srr0 = SPR_SRR0;
> - srr1 = SPR_SRR1;
> -
> - /*
> - * check for special resume at 0x100 from doze/nap/sleep/winkle on
> - * P7/P8/P9
> - */
> - if (env->resume_as_sreset) {
> - excp = powerpc_reset_wakeup(cs, env, excp, &msr);
> - }
> -
> - /*
> - * Hypervisor emulation assistance interrupt only exists on server
> - * arch 2.05 server or later. We also don't want to generate it if
> - * we don't have HVB in msr_mask (PAPR mode).
> - */
> - if (excp == POWERPC_EXCP_HV_EMU
> -#if defined(TARGET_PPC64)
> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
> -#endif /* defined(TARGET_PPC64) */
> -
> - ) {
> - excp = POWERPC_EXCP_PROGRAM;
> - }
> -
> -#ifdef TARGET_PPC64
> - /*
> - * SPEU and VPU share the same IVOR but they exist in different
> - * processors. SPEU is e500v1/2 only and VPU is e6500 only.
> - */
> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
> - excp = POWERPC_EXCP_SPEU;
> - }
> -#endif
> -
> - vector = env->excp_vectors[excp];
> - if (vector == (target_ulong)-1ULL) {
> - cpu_abort(cs, "Raised an exception without defined vector %d\n",
> - excp);
> - }
> -
> - vector |= env->excp_prefix;
> -
> - switch (excp) {
> - case POWERPC_EXCP_CRITICAL: /* Critical input */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_6xx:
> - break;
> - default:
> - goto excp_invalid;
> - }
> - break;
> - case POWERPC_EXCP_MCHECK: /* Machine check exception */
> - if (msr_me == 0) {
> - /*
> - * Machine check exception is not enabled. Enter
> - * checkstop state.
> - */
> - fprintf(stderr, "Machine check while not allowed. "
> - "Entering checkstop state\n");
> - if (qemu_log_separate()) {
> - qemu_log("Machine check while not allowed. "
> - "Entering checkstop state\n");
> - }
> - cs->halted = 1;
> - cpu_interrupt_exittb(cs);
> - }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - }
> -
> - /* machine check exceptions don't have ME set */
> - new_msr &= ~((target_ulong)1 << MSR_ME);
> -
> - /* XXX: should also have something loaded in DAR / DSISR */
> - switch (excp_model) {
> - case POWERPC_EXCP_40x:
> - srr0 = SPR_40x_SRR2;
> - srr1 = SPR_40x_SRR3;
> - break;
> - case POWERPC_EXCP_BOOKE:
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_MCSRR0;
> - srr1 = SPR_BOOKE_MCSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> - break;
> - default:
> - break;
> - }
> - break;
> - case POWERPC_EXCP_DSI: /* Data storage exception */
> - trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
> - break;
> - case POWERPC_EXCP_ISI: /* Instruction storage exception */
> - trace_ppc_excp_isi(msr, env->nip);
> - msr |= env->error_code;
> - break;
> - case POWERPC_EXCP_EXTERNAL: /* External input */
> - {
> - bool lpes0;
> -
> - cs = CPU(cpu);
> -
> - /*
> - * Exception targeting modifiers
> - *
> - * LPES0 is supported on POWER7/8/9
> - * LPES1 is not supported (old iSeries mode)
> - *
> - * On anything else, we behave as if LPES0 is 1
> - * (externals don't alter MSR:HV)
> - */
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_POWER7 ||
> - excp_model == POWERPC_EXCP_POWER8 ||
> - excp_model == POWERPC_EXCP_POWER9 ||
> - excp_model == POWERPC_EXCP_POWER10) {
> - lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
> - } else
> -#endif /* defined(TARGET_PPC64) */
> - {
> - lpes0 = true;
> - }
> -
> - if (!lpes0) {
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - }
> - if (env->mpic_proxy) {
> - /* IACK the IRQ on delivery */
> - env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
> - }
> - break;
> - }
> - case POWERPC_EXCP_ALIGN: /* Alignment exception */
> - /* Get rS/rD and rA from faulting opcode */
> - /*
> - * Note: the opcode fields will not be set properly for a
> - * direct store load/store, but nobody cares as nobody
> - * actually uses direct store segments.
> - */
> - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
> - break;
> - case POWERPC_EXCP_PROGRAM: /* Program exception */
> - switch (env->error_code & ~0xF) {
> - case POWERPC_EXCP_FP:
> - if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
> - trace_ppc_excp_fp_ignore();
> - cs->exception_index = POWERPC_EXCP_NONE;
> - env->error_code = 0;
> - return;
> - }
> -
> - /*
> - * FP exceptions always have NIP pointing to the faulting
> - * instruction, so always use store_next and claim we are
> - * precise in the MSR.
> - */
> - msr |= 0x00100000;
> - env->spr[SPR_BOOKE_ESR] = ESR_FP;
> - break;
> - case POWERPC_EXCP_INVAL:
> - trace_ppc_excp_inval(env->nip);
> - msr |= 0x00080000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> - break;
> - case POWERPC_EXCP_PRIV:
> - msr |= 0x00040000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PPR;
> - break;
> - case POWERPC_EXCP_TRAP:
> - msr |= 0x00020000;
> - env->spr[SPR_BOOKE_ESR] = ESR_PTR;
> - break;
> - default:
> - /* Should never occur */
> - cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> - env->error_code);
> - break;
> - }
> - break;
> - case POWERPC_EXCP_SYSCALL: /* System call exception */
> - lev = env->error_code;
> -
> - if ((lev == 1) && cpu->vhyp) {
> - dump_hcall(env);
> - } else {
> - dump_syscall(env);
> - }
> -
> - /*
> - * We need to correct the NIP which in this case is supposed
> - * to point to the next instruction
> - */
> - env->nip += 4;
> -
> - /* "PAPR mode" built-in hypercall emulation */
> - if ((lev == 1) && cpu->vhyp) {
> - PPCVirtualHypervisorClass *vhc =
> - PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> - vhc->hypercall(cpu->vhyp, cpu);
> - return;
> - }
> - if (lev == 1) {
> - new_msr |= (target_ulong)MSR_HVB;
> - }
> - break;
> - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
> - lev = env->error_code;
> - dump_syscall(env);
> - env->nip += 4;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -
> - vector += lev * 0x20;
> -
> - env->lr = env->nip;
> - env->ctr = msr;
> - break;
> - case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
> - case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> - case POWERPC_EXCP_DECR: /* Decrementer exception */
> - break;
> - case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> - /* FIT on 4xx */
> - trace_ppc_excp_print("FIT");
> - break;
> - case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> - trace_ppc_excp_print("WDT");
> - switch (excp_model) {
> - case POWERPC_EXCP_BOOKE:
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - default:
> - break;
> - }
> - break;
> - case POWERPC_EXCP_DTLB: /* Data TLB error */
> - case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> - break;
> - case POWERPC_EXCP_DEBUG: /* Debug interrupt */
> - if (env->flags & POWERPC_FLAG_DE) {
> - /* FIXME: choose one or the other based on CPU type */
> - srr0 = SPR_BOOKE_DSRR0;
> - srr1 = SPR_BOOKE_DSRR1;
> -
> - env->spr[SPR_BOOKE_CSRR0] = env->nip;
> - env->spr[SPR_BOOKE_CSRR1] = msr;
> -
> - /* DBSR already modified by caller */
> - } else {
> - cpu_abort(cs, "Debug exception triggered on unsupported model\n");
> - }
> - break;
> - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
> - env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> - break;
> - case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> - break;
> - case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> - srr0 = SPR_BOOKE_CSRR0;
> - srr1 = SPR_BOOKE_CSRR1;
> - break;
> - case POWERPC_EXCP_RESET: /* System reset exception */
> - /* A power-saving exception sets ME, otherwise it is unchanged */
> - if (msr_pow) {
> - /* indicate that we resumed from power save mode */
> - msr |= 0x10000;
> - new_msr |= ((target_ulong)1 << MSR_ME);
> - }
> - if (env->msr_mask & MSR_HVB) {
> - /*
> - * ISA specifies HV, but can be delivered to guest with HV
> - * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
> - */
> - new_msr |= (target_ulong)MSR_HVB;
> - } else {
> - if (msr_pow) {
> - cpu_abort(cs, "Trying to deliver power-saving system reset "
> - "exception %d with no HV support\n", excp);
> - }
> - }
> - break;
> - case POWERPC_EXCP_DSEG: /* Data segment exception */
> - case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> - case POWERPC_EXCP_TRACE: /* Trace exception */
> - break;
> - case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
> - msr |= env->error_code;
> - /* fall through */
> - case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> - case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> - case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> - case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
> - case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
> - case POWERPC_EXCP_HV_EMU:
> - case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> - break;
> - case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> - case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
> - case POWERPC_EXCP_FU: /* Facility unavailable exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
> -#endif
> - break;
> - case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
> -#ifdef TARGET_PPC64
> - env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
> - srr0 = SPR_HSRR0;
> - srr1 = SPR_HSRR1;
> - new_msr |= (target_ulong)MSR_HVB;
> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> -#endif
> - break;
> - case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
> - trace_ppc_excp_print("PIT");
> - break;
> - case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> - case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> - case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> - switch (excp_model) {
> - case POWERPC_EXCP_6xx:
> - /* Swap temporary saved registers with GPRs */
> - if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
> - new_msr |= (target_ulong)1 << MSR_TGPR;
> - hreg_swap_gpr_tgpr(env);
> - }
> - /* fall through */
> - case POWERPC_EXCP_7xx:
> - ppc_excp_debug_sw_tlb(env, excp);
> -
> - msr |= env->crf[0] << 28;
> - msr |= env->error_code; /* key, D/I, S/L bits */
> - /* Set way using a LRU mechanism */
> - msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
> - break;
> - default:
> - cpu_abort(cs, "Invalid TLB miss exception\n");
> - break;
> - }
> - break;
> - case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> - case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> - case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> - case POWERPC_EXCP_DABR: /* Data address breakpoint */
> - case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> - case POWERPC_EXCP_SMI: /* System management interrupt */
> - case POWERPC_EXCP_THERM: /* Thermal interrupt */
> - case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> - case POWERPC_EXCP_VPUA: /* Vector assist exception */
> - case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> - case POWERPC_EXCP_MAINT: /* Maintenance exception */
> - case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> - case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> - cpu_abort(cs, "%s exception not implemented\n",
> - powerpc_excp_name(excp));
> - break;
> - default:
> - excp_invalid:
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - break;
> - }
> -
> - /* Sanity check */
> - if (!(env->msr_mask & MSR_HVB)) {
> - if (new_msr & MSR_HVB) {
> - cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
> - "no HV support\n", excp);
> - }
> - if (srr0 == SPR_HSRR0) {
> - cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
> - "no HV support\n", excp);
> - }
> - }
> -
> - /*
> - * Sort out endianness of interrupt, this differs depending on the
> - * CPU, the HV mode, etc...
> - */
> - if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
> - new_msr |= (target_ulong)1 << MSR_LE;
> - }
> -
> -#if defined(TARGET_PPC64)
> - if (excp_model == POWERPC_EXCP_BOOKE) {
> - if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
> - /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
> - new_msr |= (target_ulong)1 << MSR_CM;
> - } else {
> - vector = (uint32_t)vector;
> - }
> - } else {
> - if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
> - vector = (uint32_t)vector;
> - } else {
> - new_msr |= (target_ulong)1 << MSR_SF;
> - }
> - }
> -#endif
> -
> - if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
> - /* Save PC */
> - env->spr[srr0] = env->nip;
> -
> - /* Save MSR */
> - env->spr[srr1] = msr;
> - }
> -
> - /* This can update new_msr and vector if AIL applies */
> - ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
> -
> - powerpc_set_excp_state(cpu, vector, new_msr);
> -}
> -
> static void powerpc_excp(PowerPCCPU *cpu, int excp)
> {
> CPUPPCState *env = &cpu->env;
> @@ -2139,7 +1668,7 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
> powerpc_excp_books(cpu, excp);
> break;
> default:
> - powerpc_excp_legacy(cpu, excp);
> + g_assert_not_reached();
> }
> }
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/4] target/ppc: powerpc_excp: Move common code to the caller function
2022-02-07 18:30 [PATCH 0/4] target/ppc: powerpc_excp improvements (9/9) Fabiano Rosas
2022-02-07 18:30 ` [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy Fabiano Rosas
@ 2022-02-07 18:30 ` Fabiano Rosas
2022-02-08 9:12 ` Cédric Le Goater
2022-02-07 18:30 ` [PATCH 3/4] target/ppc: Assert if MSR bits differ from msr_mask during exceptions Fabiano Rosas
2022-02-07 18:30 ` [PATCH 4/4] target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail Fabiano Rosas
3 siblings, 1 reply; 8+ messages in thread
From: Fabiano Rosas @ 2022-02-07 18:30 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
Make the cpu-specific powerpc_excp_* functions a bit simpler by moving
the bounds check and logging to powerpc_excp.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 57 +++++++---------------------------------
1 file changed, 9 insertions(+), 48 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index c6646503aa..206314aaa2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -396,14 +396,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
target_ulong msr, new_msr, vector;
int srr0, srr1;
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -554,14 +546,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -746,14 +730,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -926,14 +902,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -1121,14 +1089,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
target_ulong msr, new_msr, vector;
int srr0, srr1;
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
msr = env->msr;
/*
@@ -1348,14 +1308,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
- if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
- cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
- }
-
- qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
- " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
- excp, env->error_code);
-
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -1642,8 +1594,17 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
static void powerpc_excp(PowerPCCPU *cpu, int excp)
{
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
+ }
+
+ qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
+ " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
+ excp, env->error_code);
+
switch (env->excp_model) {
case POWERPC_EXCP_40x:
powerpc_excp_40x(cpu, excp);
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/4] target/ppc: powerpc_excp: Move common code to the caller function
2022-02-07 18:30 ` [PATCH 2/4] target/ppc: powerpc_excp: Move common code to the caller function Fabiano Rosas
@ 2022-02-08 9:12 ` Cédric Le Goater
0 siblings, 0 replies; 8+ messages in thread
From: Cédric Le Goater @ 2022-02-08 9:12 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel; +Cc: danielhb413, qemu-ppc, david
On 2/7/22 19:30, Fabiano Rosas wrote:
> Make the cpu-specific powerpc_excp_* functions a bit simpler by moving
> the bounds check and logging to powerpc_excp.
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/excp_helper.c | 57 +++++++---------------------------------
> 1 file changed, 9 insertions(+), 48 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index c6646503aa..206314aaa2 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -396,14 +396,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> target_ulong msr, new_msr, vector;
> int srr0, srr1;
>
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
>
> @@ -554,14 +546,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
> CPUPPCState *env = &cpu->env;
> target_ulong msr, new_msr, vector;
>
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
>
> @@ -746,14 +730,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
> CPUPPCState *env = &cpu->env;
> target_ulong msr, new_msr, vector;
>
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
>
> @@ -926,14 +902,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
> CPUPPCState *env = &cpu->env;
> target_ulong msr, new_msr, vector;
>
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
>
> @@ -1121,14 +1089,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
> target_ulong msr, new_msr, vector;
> int srr0, srr1;
>
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> msr = env->msr;
>
> /*
> @@ -1348,14 +1308,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
> target_ulong msr, new_msr, vector;
> int srr0, srr1, lev = -1;
>
> - if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> - cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> - }
> -
> - qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> - " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> - excp, env->error_code);
> -
> /* new srr1 value excluding must-be-zero bits */
> msr = env->msr & ~0x783f0000ULL;
>
> @@ -1642,8 +1594,17 @@ static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
>
> static void powerpc_excp(PowerPCCPU *cpu, int excp)
> {
> + CPUState *cs = CPU(cpu);
> CPUPPCState *env = &cpu->env;
>
> + if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> + }
> +
> + qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
> + " => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
> + excp, env->error_code);
> +
> switch (env->excp_model) {
> case POWERPC_EXCP_40x:
> powerpc_excp_40x(cpu, excp);
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/4] target/ppc: Assert if MSR bits differ from msr_mask during exceptions
2022-02-07 18:30 [PATCH 0/4] target/ppc: powerpc_excp improvements (9/9) Fabiano Rosas
2022-02-07 18:30 ` [PATCH 1/4] target/ppc: Remove powerpc_excp_legacy Fabiano Rosas
2022-02-07 18:30 ` [PATCH 2/4] target/ppc: powerpc_excp: Move common code to the caller function Fabiano Rosas
@ 2022-02-07 18:30 ` Fabiano Rosas
2022-02-07 18:30 ` [PATCH 4/4] target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail Fabiano Rosas
3 siblings, 0 replies; 8+ messages in thread
From: Fabiano Rosas @ 2022-02-07 18:30 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
We currently abort QEMU during the dispatch of an interrupt if we try
to set MSR_HV without having MSR_HVB in the msr_mask. I think we
should verify this for all MSR bits. There is no reason to ever have a
MSR bit set if the corresponding bit is not set in that CPU's
msr_mask.
Note that this is not about the emulated code setting reserved
bits. We clear the new_msr when starting to dispatch an exception, so
if we end up with bits not present in the msr_mask that is a QEMU
programming error.
I kept the HSRR verification for BookS because it is the only CPU
family that has HSRRs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 64 ++++------------------------------------
1 file changed, 6 insertions(+), 58 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 206314aaa2..861b7fc24d 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -364,6 +364,8 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ assert((msr & env->msr_mask) == msr);
+
/*
* We don't use hreg_store_msr here as already have treated any
* special case that could occur. Just store MSR and update hflags
@@ -372,7 +374,7 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
* will prevent setting of the HV bit which some exceptions might need
* to do.
*/
- env->msr = msr & env->msr_mask;
+ env->msr = msr;
hreg_compute_hflags(env);
env->nip = vector;
/* Reset exception state */
@@ -519,18 +521,6 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
break;
}
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
- }
-
/* Save PC */
env->spr[srr0] = env->nip;
@@ -699,14 +689,6 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
break;
}
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- }
-
/*
* Sort out endianness of interrupt, this differs depending on the
* CPU, the HV mode, etc...
@@ -871,14 +853,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
break;
}
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- }
-
/*
* Sort out endianness of interrupt, this differs depending on the
* CPU, the HV mode, etc...
@@ -1057,14 +1031,6 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
break;
}
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- }
-
/*
* Sort out endianness of interrupt, this differs depending on the
* CPU, the HV mode, etc...
@@ -1269,18 +1235,6 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
break;
}
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
- }
-
#if defined(TARGET_PPC64)
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
/* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
@@ -1551,15 +1505,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
}
/* Sanity check */
- if (!(env->msr_mask & MSR_HVB)) {
- if (new_msr & MSR_HVB) {
- cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
- "no HV support\n", excp);
- }
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
+ if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/4] target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail
2022-02-07 18:30 [PATCH 0/4] target/ppc: powerpc_excp improvements (9/9) Fabiano Rosas
` (2 preceding siblings ...)
2022-02-07 18:30 ` [PATCH 3/4] target/ppc: Assert if MSR bits differ from msr_mask during exceptions Fabiano Rosas
@ 2022-02-07 18:30 ` Fabiano Rosas
3 siblings, 0 replies; 8+ messages in thread
From: Fabiano Rosas @ 2022-02-07 18:30 UTC (permalink / raw)
To: qemu-devel; +Cc: danielhb413, qemu-ppc, clg, david
We don't really need to check for exception model while applying
AIL. We can check the lpcr_mask for the presence of
LPCR_AIL/LPCR_HAIL.
This removes one more instance of passing the exception model ID
around.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
target/ppc/excp_helper.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 861b7fc24d..116398f36a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -262,11 +262,10 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
* | a | h | 11 | 1 | 1 | h |
* +--------------------------------------------------------------------+
*/
-static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
- target_ulong msr,
- target_ulong *new_msr,
- target_ulong *vector)
+static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
+ target_ulong *new_msr, target_ulong *vector)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
bool mmu_all_on = ((msr >> MSR_IR) & 1) && ((msr >> MSR_DR) & 1);
bool hv_escalation = !(msr & MSR_HVB) && (*new_msr & MSR_HVB);
@@ -279,8 +278,13 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
return;
}
- if (excp_model == POWERPC_EXCP_POWER8 ||
- excp_model == POWERPC_EXCP_POWER9) {
+ if (!(pcc->lpcr_mask & LPCR_AIL)) {
+ /* This CPU does not have AIL */
+ return;
+ }
+
+ /* P8 & P9 */
+ if (!(pcc->lpcr_mask & LPCR_HAIL)) {
if (!mmu_all_on) {
/* AIL only works if MSR[IR] and MSR[DR] are both enabled. */
return;
@@ -303,7 +307,8 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
return;
}
- } else if (excp_model == POWERPC_EXCP_POWER10) {
+ /* P10 and up */
+ } else {
if (!mmu_all_on && !hv_escalation) {
/*
* AIL works for HV interrupts even with guest MSR[IR/DR] disabled.
@@ -328,9 +333,6 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp,
/* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */
return;
}
- } else {
- /* Other processors do not support AIL */
- return;
}
/*
@@ -1258,7 +1260,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- int excp_model = env->excp_model;
target_ulong msr, new_msr, vector;
int srr0, srr1, lev = -1;
@@ -1529,7 +1530,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
}
/* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
+ ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread