From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/39] hw/arm/xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs
Date: Tue, 8 Feb 2022 11:39:14 +0000 [thread overview]
Message-ID: <20220208113948.3217356-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220208113948.3217356-1-peter.maydell@linaro.org>
From: Francisco Iglesias <francisco.iglesias@xilinx.com>
'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for
avoiding the situation where one of the models incorrectly deasserts an
interrupt asserted from the other model (which will result in that the IRQ
is lost and will not reach guest SW).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220203151742.1457-1-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-zynqmp.h | 2 ++
hw/arm/xlnx-zynqmp.c | 14 ++++++++++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 062e637fe49..9424f81c377 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -38,6 +38,7 @@
#include "hw/dma/xlnx_csu_dma.h"
#include "hw/nvram/xlnx-bbram.h"
#include "hw/nvram/xlnx-zynqmp-efuse.h"
+#include "hw/or-irq.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -122,6 +123,7 @@ struct XlnxZynqMPState {
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
XlnxCSUDMA qspi_dma;
+ qemu_or_irq qspi_irq_orgate;
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 1c52a575aad..5fbf38c4660 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -50,6 +50,7 @@
#define LQSPI_ADDR 0xc0000000
#define QSPI_IRQ 15
#define QSPI_DMA_ADDR 0xff0f0800
+#define NUM_QSPI_IRQ_LINES 2
#define DP_ADDR 0xfd4a0000
#define DP_IRQ 113
@@ -362,6 +363,8 @@ static void xlnx_zynqmp_init(Object *obj)
}
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
+ object_initialize_child(obj, "qspi-irq-orgate",
+ &s->qspi_irq_orgate, TYPE_OR_IRQ);
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -709,6 +712,11 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
gic_spi[adma_ch_intr[i]]);
}
+ object_property_set_int(OBJECT(&s->qspi_irq_orgate),
+ "num-lines", NUM_QSPI_IRQ_LINES, &error_fatal);
+ qdev_realize(DEVICE(&s->qspi_irq_orgate), NULL, &error_fatal);
+ qdev_connect_gpio_out(DEVICE(&s->qspi_irq_orgate), 0, gic_spi[QSPI_IRQ]);
+
if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma",
OBJECT(system_memory), errp)) {
return;
@@ -718,7 +726,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0,
+ qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0));
if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
OBJECT(&s->qspi_dma), errp)) {
@@ -729,7 +738,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0,
+ qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 1));
for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i);
--
2.25.1
next prev parent reply other threads:[~2022-02-08 12:18 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-08 11:39 [PULL 00/39] target-arm queue Peter Maydell
2022-02-08 11:39 ` [PULL 01/39] target/arm: Fix sve_zcr_len_for_el for VHE mode running Peter Maydell
2022-02-08 11:39 ` [PULL 02/39] target/arm: Tidy sve_exception_el for CPACR_EL1 access Peter Maydell
2022-02-08 11:39 ` [PULL 03/39] target/arm: Fix {fp, sve}_exception_el for VHE mode running Peter Maydell
2022-02-08 11:39 ` [PULL 04/39] target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_el Peter Maydell
2022-02-08 11:39 ` Peter Maydell [this message]
2022-02-08 11:39 ` [PULL 06/39] target/arm: make psci-conduit settable after realize Peter Maydell
2022-02-08 11:39 ` [PULL 07/39] cpu.c: Make start-powered-off " Peter Maydell
2022-02-08 11:39 ` [PULL 08/39] hw/arm/boot: Support setting psci-conduit based on guest EL Peter Maydell
2022-02-08 11:39 ` [PULL 09/39] hw/arm: imx: Don't enable PSCI conduit when booting guest in EL3 Peter Maydell
2022-02-08 11:39 ` [PULL 10/39] hw/arm: allwinner: " Peter Maydell
2022-02-08 11:39 ` [PULL 11/39] hw/arm/xlnx-zcu102: " Peter Maydell
2022-02-08 11:39 ` [PULL 12/39] hw/arm/versal: Let boot.c handle PSCI enablement Peter Maydell
2022-02-08 11:39 ` [PULL 13/39] hw/arm/virt: " Peter Maydell
2022-02-08 11:39 ` [PULL 14/39] hw/arm: highbank: For EL3 guests, don't enable PSCI, start all cores Peter Maydell
2022-02-08 11:39 ` [PULL 15/39] arm: tcg: Adhere to SMCCC 1.3 section 5.2 Peter Maydell
2022-02-08 11:39 ` [PULL 16/39] hw/arm/highbank: Drop use of secure_board_setup Peter Maydell
2022-02-08 11:39 ` [PULL 17/39] hw/arm/boot: Prevent setting both psci_conduit and secure_board_setup Peter Maydell
2022-02-08 11:39 ` [PULL 18/39] hw/arm/boot: Don't write secondary boot stub if using PSCI Peter Maydell
2022-02-08 11:39 ` [PULL 19/39] hw/arm/highbank: Drop unused secondary boot stub code Peter Maydell
2022-02-08 11:39 ` [PULL 20/39] hw/arm/boot: Drop nb_cpus field from arm_boot_info Peter Maydell
2022-02-08 11:39 ` [PULL 21/39] hw/arm/boot: Drop existing dtb /psci node rather than retaining it Peter Maydell
2022-02-08 11:39 ` [PULL 22/39] hw/arm: versal-virt: Always call arm_load_kernel() Peter Maydell
2022-02-08 11:39 ` [PULL 23/39] arm: force flag recalculation when messing with DAIF Peter Maydell
2022-02-08 11:39 ` [PULL 24/39] hw/timer/armv7m_systick: Update clock source before enabling timer Peter Maydell
2022-02-08 11:39 ` [PULL 25/39] hw/arm/smmuv3: Fix device reset Peter Maydell
2022-02-08 11:39 ` [PULL 26/39] hw/intc/arm_gicv3_its: Use address_space_map() to access command queue packets Peter Maydell
2022-02-08 11:39 ` [PULL 27/39] hw/intc/arm_gicv3_its: Keep DTEs as a struct, not a raw uint64_t Peter Maydell
2022-02-08 11:39 ` [PULL 28/39] hw/intc/arm_gicv3_its: Pass DTEntry to update_dte() Peter Maydell
2022-02-08 11:39 ` [PULL 29/39] hw/intc/arm_gicv3_its: Keep CTEs as a struct, not a raw uint64_t Peter Maydell
2022-02-08 11:39 ` [PULL 30/39] hw/intc/arm_gicv3_its: Pass CTEntry to update_cte() Peter Maydell
2022-02-08 11:39 ` [PULL 31/39] hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite() Peter Maydell
2022-02-08 11:39 ` [PULL 32/39] hw/intc/arm_gicv3_its: Avoid nested ifs in get_ite() Peter Maydell
2022-02-08 11:39 ` [PULL 33/39] hw/intc/arm_gicv3_its: Pass ITE values back from get_ite() via a struct Peter Maydell
2022-02-08 11:39 ` [PULL 34/39] hw/intc/arm_gicv3_its: Make update_ite() use ITEntry Peter Maydell
2022-02-08 11:39 ` [PULL 35/39] hw/intc/arm_gicv3_its: Drop TableDesc and CmdQDesc valid fields Peter Maydell
2022-02-08 11:39 ` [PULL 36/39] hw/intc/arm_gicv3_its: In MAPC with V=0, don't check rdbase field Peter Maydell
2022-02-08 11:39 ` [PULL 37/39] hw/intc/arm_gicv3_its: Don't allow intid 1023 in MAPI/MAPTI Peter Maydell
2022-02-08 11:39 ` [PULL 38/39] hw/intc/arm_gicv3_its: Split error checks Peter Maydell
2022-02-08 11:39 ` [PULL 39/39] hw/sensor: Add lsm303dlhc magnetometer device Peter Maydell
2022-02-08 15:03 ` [PULL 00/39] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220208113948.3217356-6-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).