From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, tsimpson@quicinc.com, bcain@quicinc.com,
mlambert@quicinc.com, babush@rev.ng, nizzo@rev.ng,
richard.henderson@linaro.org
Subject: [PATCH v8 03/12] target/hexagon: make slot number an unsigned
Date: Wed, 9 Feb 2022 18:03:03 +0100 [thread overview]
Message-ID: <20220209170312.30662-4-anjo@rev.ng> (raw)
In-Reply-To: <20220209170312.30662-1-anjo@rev.ng>
From: Paolo Montesel <babush@rev.ng>
Signed-off-by: Alessandro Di Federico <ale@rev.ng>
Signed-off-by: Paolo Montesel <babush@rev.ng>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/genptr.c | 24 +++++++++++++-----------
target/hexagon/macros.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 4419d30e23..2f73300c90 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -30,7 +30,8 @@
#include "gen_tcg.h"
#include "gen_tcg_hvx.h"
-static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
+static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
+ uint32_t slot)
{
TCGv zero = tcg_constant_tl(0);
TCGv slot_mask = tcg_temp_new();
@@ -62,7 +63,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
}
}
-static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
+static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
+ uint32_t slot)
{
TCGv val32 = tcg_temp_new();
TCGv zero = tcg_constant_tl(0);
@@ -390,7 +392,7 @@ static inline void gen_store_conditional8(DisasContext *ctx,
tcg_gen_movi_tl(hex_llsc_addr, ~0);
}
-static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
+static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], width);
@@ -398,49 +400,49 @@ static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
}
static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
gen_store32(vaddr, src, 1, slot);
ctx->store_width[slot] = 1;
}
static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store1(cpu_env, vaddr, tmp, ctx, slot);
}
static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
gen_store32(vaddr, src, 2, slot);
ctx->store_width[slot] = 2;
}
static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store2(cpu_env, vaddr, tmp, ctx, slot);
}
static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
gen_store32(vaddr, src, 4, slot);
ctx->store_width[slot] = 4;
}
static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store4(cpu_env, vaddr, tmp, ctx, slot);
}
static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
@@ -449,7 +451,7 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
}
static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
- DisasContext *ctx, int slot)
+ DisasContext *ctx, uint32_t slot)
{
TCGv_i64 tmp = tcg_constant_i64(src);
gen_store8(cpu_env, vaddr, tmp, ctx, slot);
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 19d103cad5..3a64357090 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -185,7 +185,7 @@
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
#ifdef QEMU_GENERATE
-static inline void gen_pred_cancel(TCGv pred, int slot_num)
+static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
{
TCGv slot_mask = tcg_temp_new();
TCGv tmp = tcg_temp_new();
--
2.34.1
next prev parent reply other threads:[~2022-02-09 17:21 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 17:03 [PATCH v8 00/12] target/hexagon: introduce idef-parser Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 01/12] target/hexagon: update MAINTAINERS for idef-parser Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 02/12] target/hexagon: import README " Anton Johansson via
2022-02-09 17:03 ` Anton Johansson via [this message]
2022-02-09 17:03 ` [PATCH v8 04/12] target/hexagon: make helper functions non-static Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 05/12] target/hexagon: introduce new helper functions Anton Johansson via
2022-03-21 18:28 ` Taylor Simpson
2022-02-09 17:03 ` [PATCH v8 06/12] target/hexagon: expose next PC in DisasContext Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 07/12] target/hexagon: prepare input for the idef-parser Anton Johansson via
2022-03-21 18:33 ` Taylor Simpson
2022-02-09 17:03 ` [PATCH v8 08/12] target/hexagon: import flex/bison to docker files Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 09/12] target/hexagon: import lexer for idef-parser Anton Johansson via
2022-03-21 18:40 ` Taylor Simpson
2022-02-09 17:03 ` [PATCH v8 10/12] target/hexagon: import parser " Anton Johansson via
2022-04-11 15:20 ` Taylor Simpson
2022-04-12 15:10 ` Anton Johansson via
2022-04-12 18:41 ` Taylor Simpson
2022-04-21 11:50 ` Anton Johansson via
2022-04-21 14:22 ` Taylor Simpson
2022-04-21 16:38 ` Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 11/12] target/hexagon: call idef-parser functions Anton Johansson via
2022-02-09 17:03 ` [PATCH v8 12/12] target/hexagon: import additional tests Anton Johansson via
2022-03-21 18:58 ` Taylor Simpson
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