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From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Stafford Horne <shorne@gmail.com>, Jia Liu <proljc@gmail.com>
Subject: [PATCH 1/4] hw/openrisc/openrisc_sim: Create machine state for or1ksim
Date: Thu, 10 Feb 2022 15:30:06 +0900	[thread overview]
Message-ID: <20220210063009.1048751-2-shorne@gmail.com> (raw)
In-Reply-To: <20220210063009.1048751-1-shorne@gmail.com>

This will allow us to attach machine state attributes like
the device tree fdt.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 hw/openrisc/openrisc_sim.c | 31 +++++++++++++++++++++++++++++--
 1 file changed, 29 insertions(+), 2 deletions(-)

diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 73fe383c2d..b83cc1c191 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -37,6 +37,18 @@
 
 #define KERNEL_LOAD_ADDR 0x100
 
+#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
+#define OR1KSIM_MACHINE(obj) \
+    OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
+
+typedef struct Or1ksimState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+
+} Or1ksimState;
+
 static struct openrisc_boot_info {
     uint32_t bootstrap_pc;
 } boot_info;
@@ -141,6 +153,7 @@ static void openrisc_sim_init(MachineState *machine)
     ram_addr_t ram_size = machine->ram_size;
     const char *kernel_filename = machine->kernel_filename;
     OpenRISCCPU *cpus[2] = {};
+    Or1ksimState *s = OR1KSIM_MACHINE(machine);
     MemoryRegion *ram;
     qemu_irq serial_irq;
     int n;
@@ -183,8 +196,10 @@ static void openrisc_sim_init(MachineState *machine)
     openrisc_load_kernel(ram_size, kernel_filename);
 }
 
-static void openrisc_sim_machine_init(MachineClass *mc)
+static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
 {
+    MachineClass *mc = MACHINE_CLASS(oc);
+
     mc->desc = "or1k simulation";
     mc->init = openrisc_sim_init;
     mc->max_cpus = 2;
@@ -192,4 +207,16 @@ static void openrisc_sim_machine_init(MachineClass *mc)
     mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
 }
 
-DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
+static const TypeInfo or1ksim_machine_typeinfo = {
+    .name       = TYPE_OR1KSIM_MACHINE,
+    .parent     = TYPE_MACHINE,
+    .class_init = openrisc_sim_machine_init,
+    .instance_size = sizeof(Or1ksimState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+    type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
-- 
2.31.1



  reply	other threads:[~2022-02-10  6:53 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-10  6:30 [PATCH 0/4] OpenRISC Device Tree Support Stafford Horne
2022-02-10  6:30 ` Stafford Horne [this message]
2022-02-10 11:05   ` [PATCH 1/4] hw/openrisc/openrisc_sim: Create machine state for or1ksim Philippe Mathieu-Daudé via
2022-02-10 12:16     ` Stafford Horne
2022-02-10  6:30 ` [PATCH 2/4] hw/openrisc/openrisc_sim: Paramatarize initialization Stafford Horne
2022-02-10 11:07   ` Philippe Mathieu-Daudé via
2022-02-10 12:18     ` Stafford Horne
2022-02-10  6:30 ` [PATCH 3/4] hw/openrisc/openrisc_sim; Add support for loading a decice tree Stafford Horne
2022-02-10 11:10   ` Philippe Mathieu-Daudé via
2022-02-10 12:34     ` Stafford Horne
2022-02-17 18:18   ` Peter Maydell
2022-02-17 21:39     ` Stafford Horne
2022-02-18 11:46       ` Peter Maydell
2022-02-10  6:30 ` [PATCH 4/4] hw/openrisc/openrisc_sim: Add support for initrd loading Stafford Horne

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