From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL 12/34] tcg/ppc: Support raising sigbus for user-only
Date: Fri, 11 Feb 2022 12:30:37 +1100 [thread overview]
Message-ID: <20220211013059.17994-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220211013059.17994-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.h | 2 -
tcg/ppc/tcg-target.c.inc | 98 ++++++++++++++++++++++++++++++++++++----
2 files changed, 90 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 0943192cde..c775c97b61 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -182,9 +182,7 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
-#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
-#endif
#define TCG_TARGET_NEED_POOL_LABELS
#endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 9e79a7edee..dea24f23c4 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -24,6 +24,7 @@
#include "elf.h"
#include "../tcg-pool.c.inc"
+#include "../tcg-ldst.c.inc"
/*
* Standardize on the _CALL_FOO symbols used by GCC:
@@ -1881,7 +1882,8 @@ void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
}
}
-static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
+static void tcg_out_call_int(TCGContext *s, int lk,
+ const tcg_insn_unit *target)
{
#ifdef _CALL_AIX
/* Look through the descriptor. If the branch is in range, and we
@@ -1892,7 +1894,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
if (in_range_b(diff) && toc == (uint32_t)toc) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
- tcg_out_b(s, LK, tgt);
+ tcg_out_b(s, lk, tgt);
} else {
/* Fold the low bits of the constant into the addresses below. */
intptr_t arg = (intptr_t)target;
@@ -1907,7 +1909,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
- tcg_out32(s, BCCTR | BO_ALWAYS | LK);
+ tcg_out32(s, BCCTR | BO_ALWAYS | lk);
}
#elif defined(_CALL_ELF) && _CALL_ELF == 2
intptr_t diff;
@@ -1921,16 +1923,21 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
diff = tcg_pcrel_diff(s, target);
if (in_range_b(diff)) {
- tcg_out_b(s, LK, target);
+ tcg_out_b(s, lk, target);
} else {
tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
- tcg_out32(s, BCCTR | BO_ALWAYS | LK);
+ tcg_out32(s, BCCTR | BO_ALWAYS | lk);
}
#else
- tcg_out_b(s, LK, target);
+ tcg_out_b(s, lk, target);
#endif
}
+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
+{
+ tcg_out_call_int(s, LK, target);
+}
+
static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = {
[MO_UB] = LBZX,
[MO_UW] = LHZX,
@@ -1960,8 +1967,6 @@ static const uint32_t qemu_exts_opc[4] = {
};
#if defined (CONFIG_SOFTMMU)
-#include "../tcg-ldst.c.inc"
-
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
@@ -2227,6 +2232,71 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
tcg_out_b(s, 0, lb->raddr);
return true;
}
+#else
+
+static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
+ TCGReg addrhi, unsigned a_bits)
+{
+ unsigned a_mask = (1 << a_bits) - 1;
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->addrlo_reg = addrlo;
+ label->addrhi_reg = addrhi;
+
+ /* We are expecting a_bits to max out at 7, much lower than ANDI. */
+ tcg_debug_assert(a_bits < 16);
+ tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask));
+
+ label->label_ptr[0] = s->code_ptr;
+ tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK);
+
+ label->raddr = tcg_splitwx_to_rx(s->code_ptr);
+}
+
+static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
+ return false;
+ }
+
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ TCGReg arg = TCG_REG_R4;
+#ifdef TCG_TARGET_CALL_ALIGN_ARGS
+ arg |= 1;
+#endif
+ if (l->addrlo_reg != arg) {
+ tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
+ } else if (l->addrhi_reg != arg + 1) {
+ tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg);
+ tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1);
+ tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0);
+ }
+ } else {
+ tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg);
+ }
+ tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0);
+
+ /* "Tail call" to the helper, with the return address back inline. */
+ tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld
+ : helper_unaligned_st));
+ return true;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
#endif /* SOFTMMU */
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
@@ -2238,6 +2308,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
#ifdef CONFIG_SOFTMMU
int mem_index;
tcg_insn_unit *label_ptr;
+#else
+ unsigned a_bits;
#endif
datalo = *args++;
@@ -2258,6 +2330,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
rbase = TCG_REG_R3;
#else /* !CONFIG_SOFTMMU */
+ a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
+ }
rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
@@ -2313,6 +2389,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
#ifdef CONFIG_SOFTMMU
int mem_index;
tcg_insn_unit *label_ptr;
+#else
+ unsigned a_bits;
#endif
datalo = *args++;
@@ -2333,6 +2411,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
rbase = TCG_REG_R3;
#else /* !CONFIG_SOFTMMU */
+ a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
+ }
rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
--
2.25.1
next prev parent reply other threads:[~2022-02-11 1:41 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 1:30 [PULL 00/34] tcg patch queue Richard Henderson
2022-02-11 1:30 ` [PULL 01/34] common-user/host/sparc64: Fix safe_syscall_base Richard Henderson
2022-02-11 1:30 ` [PULL 02/34] linux-user: Introduce host_signal_mask Richard Henderson
2022-02-11 1:30 ` [PULL 03/34] linux-user: Introduce host_sigcontext Richard Henderson
2022-02-11 1:30 ` [PULL 04/34] linux-user: Move sparc/host-signal.h to sparc64/host-signal.h Richard Henderson
2022-02-11 1:30 ` [PULL 05/34] linux-user/include/host/sparc64: Fix host_sigcontext Richard Henderson
2022-02-11 1:30 ` [PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush Richard Henderson
2022-02-11 1:30 ` [PULL 07/34] softmmu/cpus: Check if the cpu work list is empty atomically Richard Henderson
2022-02-11 1:30 ` [PULL 08/34] replay: use CF_NOIRQ for special exception-replaying TB Richard Henderson
2022-02-11 1:30 ` [PULL 09/34] tcg/loongarch64: Fix fallout from recent MO_Q renaming Richard Henderson
2022-02-11 1:30 ` [PULL 10/34] tcg/i386: Support raising sigbus for user-only Richard Henderson
2022-02-11 1:30 ` [PULL 11/34] tcg/aarch64: " Richard Henderson
2022-02-11 1:30 ` Richard Henderson [this message]
2022-02-11 1:30 ` [PULL 13/34] tcg/riscv: " Richard Henderson
2022-02-11 1:30 ` [PULL 14/34] tcg/s390x: " Richard Henderson
2022-02-11 1:30 ` [PULL 15/34] tcg/tci: " Richard Henderson
2022-02-11 1:30 ` [PULL 16/34] tcg/loongarch64: " Richard Henderson
2022-02-11 1:30 ` [PULL 17/34] tcg/arm: Drop support for armv4 and armv5 hosts Richard Henderson
2022-02-11 1:30 ` [PULL 18/34] tcg/arm: Remove use_armv5t_instructions Richard Henderson
2022-02-11 1:30 ` [PULL 19/34] tcg/arm: Remove use_armv6_instructions Richard Henderson
2022-02-11 1:30 ` [PULL 20/34] tcg/arm: Check alignment for ldrd and strd Richard Henderson
2022-02-11 1:30 ` [PULL 21/34] tcg/arm: Support unaligned access for softmmu Richard Henderson
2022-02-11 1:30 ` [PULL 22/34] tcg/arm: Reserve a register for guest_base Richard Henderson
2022-02-11 1:30 ` [PULL 23/34] tcg/arm: Support raising sigbus for user-only Richard Henderson
2022-02-11 1:30 ` [PULL 24/34] tcg/mips: Support unaligned access " Richard Henderson
2022-02-11 1:30 ` [PULL 25/34] tcg/mips: Support unaligned access for softmmu Richard Henderson
2022-02-11 1:30 ` [PULL 26/34] tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 Richard Henderson
2022-02-11 1:30 ` [PULL 27/34] tcg/sparc: Split out tcg_out_movi_imm32 Richard Henderson
2022-02-11 1:30 ` [PULL 28/34] tcg/sparc: Add scratch argument to tcg_out_movi_int Richard Henderson
2022-02-11 1:30 ` [PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants Richard Henderson
2022-02-11 1:30 ` [PULL 30/34] tcg/sparc: Convert patch_reloc to return bool Richard Henderson
2022-02-11 1:30 ` [PULL 31/34] tcg/sparc: Use the constant pool for 64-bit constants Richard Henderson
2022-02-11 1:30 ` [PULL 32/34] tcg/sparc: Add tcg_out_jmpl_const for better tail calls Richard Henderson
2022-02-11 1:30 ` [PULL 33/34] tcg/sparc: Support unaligned access for user-only Richard Henderson
2022-02-11 1:30 ` [PULL 34/34] tests/tcg/multiarch: Add sigbus.c Richard Henderson
2022-02-14 19:53 ` [PULL 00/34] tcg patch queue Peter Maydell
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