From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL 14/34] tcg/s390x: Support raising sigbus for user-only
Date: Fri, 11 Feb 2022 12:30:39 +1100 [thread overview]
Message-ID: <20220211013059.17994-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220211013059.17994-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.h | 2 --
tcg/s390x/tcg-target.c.inc | 59 ++++++++++++++++++++++++++++++++++++--
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 527ada0f63..69217d995b 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -178,9 +178,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
/* no need to flush icache explicitly */
}
-#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
-#endif
#define TCG_TARGET_NEED_POOL_LABELS
#endif
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index b12fbfda63..d56c1e51e4 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -29,6 +29,7 @@
#error "unsupported code generation mode"
#endif
+#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
#include "elf.h"
@@ -136,6 +137,7 @@ typedef enum S390Opcode {
RI_OIHL = 0xa509,
RI_OILH = 0xa50a,
RI_OILL = 0xa50b,
+ RI_TMLL = 0xa701,
RIE_CGIJ = 0xec7c,
RIE_CGRJ = 0xec64,
@@ -1804,8 +1806,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
}
#if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.c.inc"
-
/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
@@ -1942,6 +1942,53 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
return true;
}
#else
+static void tcg_out_test_alignment(TCGContext *s, bool is_ld,
+ TCGReg addrlo, unsigned a_bits)
+{
+ unsigned a_mask = (1 << a_bits) - 1;
+ TCGLabelQemuLdst *l = new_ldst_label(s);
+
+ l->is_ld = is_ld;
+ l->addrlo_reg = addrlo;
+
+ /* We are expecting a_bits to max out at 7, much lower than TMLL. */
+ tcg_debug_assert(a_bits < 16);
+ tcg_out_insn(s, RI, TMLL, addrlo, a_mask);
+
+ tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */
+ l->label_ptr[0] = s->code_ptr;
+ s->code_ptr += 1;
+
+ l->raddr = tcg_splitwx_to_rx(s->code_ptr);
+}
+
+static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL,
+ (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, l->addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
+
+ /* "Tail call" to the helper, with the return address back inline. */
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R14, (uintptr_t)l->raddr);
+ tgen_gotoi(s, S390_CC_ALWAYS, (const void *)(l->is_ld ? helper_unaligned_ld
+ : helper_unaligned_st));
+ return true;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
TCGReg *index_reg, tcg_target_long *disp)
{
@@ -1980,7 +2027,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
#else
TCGReg index_reg;
tcg_target_long disp;
+ unsigned a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, true, addr_reg, a_bits);
+ }
tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
#endif
@@ -2007,7 +2058,11 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
#else
TCGReg index_reg;
tcg_target_long disp;
+ unsigned a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, false, addr_reg, a_bits);
+ }
tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
#endif
--
2.25.1
next prev parent reply other threads:[~2022-02-11 2:00 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 1:30 [PULL 00/34] tcg patch queue Richard Henderson
2022-02-11 1:30 ` [PULL 01/34] common-user/host/sparc64: Fix safe_syscall_base Richard Henderson
2022-02-11 1:30 ` [PULL 02/34] linux-user: Introduce host_signal_mask Richard Henderson
2022-02-11 1:30 ` [PULL 03/34] linux-user: Introduce host_sigcontext Richard Henderson
2022-02-11 1:30 ` [PULL 04/34] linux-user: Move sparc/host-signal.h to sparc64/host-signal.h Richard Henderson
2022-02-11 1:30 ` [PULL 05/34] linux-user/include/host/sparc64: Fix host_sigcontext Richard Henderson
2022-02-11 1:30 ` [PULL 06/34] accel/tcg: Optimize jump cache flush during tlb range flush Richard Henderson
2022-02-11 1:30 ` [PULL 07/34] softmmu/cpus: Check if the cpu work list is empty atomically Richard Henderson
2022-02-11 1:30 ` [PULL 08/34] replay: use CF_NOIRQ for special exception-replaying TB Richard Henderson
2022-02-11 1:30 ` [PULL 09/34] tcg/loongarch64: Fix fallout from recent MO_Q renaming Richard Henderson
2022-02-11 1:30 ` [PULL 10/34] tcg/i386: Support raising sigbus for user-only Richard Henderson
2022-02-11 1:30 ` [PULL 11/34] tcg/aarch64: " Richard Henderson
2022-02-11 1:30 ` [PULL 12/34] tcg/ppc: " Richard Henderson
2022-02-11 1:30 ` [PULL 13/34] tcg/riscv: " Richard Henderson
2022-02-11 1:30 ` Richard Henderson [this message]
2022-02-11 1:30 ` [PULL 15/34] tcg/tci: " Richard Henderson
2022-02-11 1:30 ` [PULL 16/34] tcg/loongarch64: " Richard Henderson
2022-02-11 1:30 ` [PULL 17/34] tcg/arm: Drop support for armv4 and armv5 hosts Richard Henderson
2022-02-11 1:30 ` [PULL 18/34] tcg/arm: Remove use_armv5t_instructions Richard Henderson
2022-02-11 1:30 ` [PULL 19/34] tcg/arm: Remove use_armv6_instructions Richard Henderson
2022-02-11 1:30 ` [PULL 20/34] tcg/arm: Check alignment for ldrd and strd Richard Henderson
2022-02-11 1:30 ` [PULL 21/34] tcg/arm: Support unaligned access for softmmu Richard Henderson
2022-02-11 1:30 ` [PULL 22/34] tcg/arm: Reserve a register for guest_base Richard Henderson
2022-02-11 1:30 ` [PULL 23/34] tcg/arm: Support raising sigbus for user-only Richard Henderson
2022-02-11 1:30 ` [PULL 24/34] tcg/mips: Support unaligned access " Richard Henderson
2022-02-11 1:30 ` [PULL 25/34] tcg/mips: Support unaligned access for softmmu Richard Henderson
2022-02-11 1:30 ` [PULL 26/34] tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 Richard Henderson
2022-02-11 1:30 ` [PULL 27/34] tcg/sparc: Split out tcg_out_movi_imm32 Richard Henderson
2022-02-11 1:30 ` [PULL 28/34] tcg/sparc: Add scratch argument to tcg_out_movi_int Richard Henderson
2022-02-11 1:30 ` [PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants Richard Henderson
2022-02-11 1:30 ` [PULL 30/34] tcg/sparc: Convert patch_reloc to return bool Richard Henderson
2022-02-11 1:30 ` [PULL 31/34] tcg/sparc: Use the constant pool for 64-bit constants Richard Henderson
2022-02-11 1:30 ` [PULL 32/34] tcg/sparc: Add tcg_out_jmpl_const for better tail calls Richard Henderson
2022-02-11 1:30 ` [PULL 33/34] tcg/sparc: Support unaligned access for user-only Richard Henderson
2022-02-11 1:30 ` [PULL 34/34] tests/tcg/multiarch: Add sigbus.c Richard Henderson
2022-02-14 19:53 ` [PULL 00/34] tcg patch queue Peter Maydell
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