[PATCH v11 0/4] PMU-EBB support for PPC64 TCG

[Daniel Henrique Barboza <danielhb413@gmail.com>]

Hi,

This new version makes a few modifications to make the EBB support more
generic.

A new patch (3) was added to implement PPC_INTERRUPT_EBB and its two
internal exceptions described by ISA v3.1: POWERPC_EXCP_PERFM_EBB and
POWERPC_EXCP_EXTERNAL_EBB. When receiving an EBB interrupt we check
BESCR bits to fire the appropriate exception. They are doing the same
thing ATM (clear GE and enter the branch with env->nip = SPR_EBBHR).
PPC_INTERRUPT_EBB will be used for the future XIVE IC EBB lane as well.

Patch 4 (previous 3) contains the helpers used by the PMU to fire the
PERFM_EBB exception, but now we're checking msr_pr and either throwing
the exception immediately or queueing it up for later via
PPC_INTERRUPT_EBB.  This change covers all the race conditions that the
kernel EBB selftests seems to trigger, and without using ppc_set_irq()
to handle BQL.

Changes from v10:
- patch 1:
  * added David's r-b
- patch 3 (new):
  * add PPC_INTERRUPT_EBB, POWERPC_EXCP_PERFM_EBB and
    POWERPC_EXCP_EXTERNAL_EBB
- patch 4:
  * all EBB bits are now being checked in the helper
  * a new static do_ebb() helper was created to handle the common
    EBB logic
  * we're now checking msr_pr and either throwing the exception immediately
    or queueing it for later using PPC_INTERRUPT_EBB
  * ppc_set_irq() call was removed
- v10 link: https://lists.gnu.org/archive/html/qemu-devel/2022-02/msg01856.html


Daniel Henrique Barboza (4):
  target/ppc: fix indent of function parameters
  target/ppc: finalize pre-EBB PMU logic
  target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions
  target/ppc: trigger PERFM EBBs from power8-pmu.c

 target/ppc/cpu.h         |  5 ++-
 target/ppc/cpu_init.c    |  4 ++
 target/ppc/excp_helper.c | 89 ++++++++++++++++++++++++++++++++++++++--
 target/ppc/helper.h      |  1 +
 target/ppc/power8-pmu.c  | 39 ++++++++++++++++--
 5 files changed, 129 insertions(+), 9 deletions(-)

-- 
2.34.1