From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Philipp Tomsich <philipp.tomsich@vrull.eu>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 09/40] target/riscv: Add XVentanaCondOps custom extension
Date: Sat, 12 Feb 2022 10:00:00 +1000 [thread overview]
Message-ID: <20220212000031.3946524-10-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220212000031.3946524-1-alistair.francis@opensource.wdc.com>
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a guard-function (has_XVentanaCondOps_p)
and the decoder function to the table of decoders, enabling the
support for the XVentanaCondOps extension.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220202005249.3566542-7-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 ++
target/riscv/XVentanaCondOps.decode | 25 ++++++++++++
target/riscv/cpu.c | 3 ++
target/riscv/translate.c | 12 ++++++
.../insn_trans/trans_xventanacondops.c.inc | 39 +++++++++++++++++++
target/riscv/meson.build | 1 +
6 files changed, 83 insertions(+)
create mode 100644 target/riscv/XVentanaCondOps.decode
create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1175915c0d..aacc997d56 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -329,6 +329,9 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
+ /* Vendor-specific custom extensions */
+ bool ext_XVentanaCondOps;
+
char *priv_spec;
char *user_spec;
char *bext_spec;
diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCondOps.decode
new file mode 100644
index 0000000000..5aef7c3d72
--- /dev/null
+++ b/target/riscv/XVentanaCondOps.decode
@@ -0,0 +1,25 @@
+#
+# RISC-V translation routines for the XVentanaCondOps extension
+#
+# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference: VTx-family custom instructions
+# Custom ISA extensions for Ventana Micro Systems RISC-V cores
+# (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf)
+
+# Fields
+%rs2 20:5
+%rs1 15:5
+%rd 7:5
+
+# Argument sets
+&r rd rs1 rs2 !extern
+
+# Formats
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
+
+# *** RV64 Custom-3 Extension ***
+vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r
+vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5ada71e5bf..1238aabe3f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -733,6 +733,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ /* Vendor-specific custom extensions */
+ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
+
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 30b1b68341..eaf5a72c81 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -116,6 +116,14 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
return true;
}
+#define MATERIALISE_EXT_PREDICATE(ext) \
+ static bool has_ ## ext ## _p(DisasContext *ctx) \
+ { \
+ return ctx->cfg_ptr->ext_ ## ext ; \
+ }
+
+MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
+
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -854,9 +862,12 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
+#include "insn_trans/trans_xventanacondops.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
+/* Include decoders for factored-out extensions */
+#include "decode-XVentanaCondOps.c.inc"
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
@@ -869,6 +880,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
bool (*decode_func)(DisasContext *, uint32_t);
} decoders[] = {
{ always_true_p, decode_insn32 },
+ { has_XVentanaCondOps_p, decode_XVentanaCodeOps },
};
/* Check for compressed insn */
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
new file mode 100644
index 0000000000..16849e6d4e
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
@@ -0,0 +1,39 @@
+/*
+ * RISC-V translation routines for the XVentanaCondOps extension.
+ *
+ * Copyright (c) 2021-2022 VRULL GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
+{
+ return gen_vt_condmask(ctx, a, TCG_COND_NE);
+}
+
+static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
+{
+ return gen_vt_condmask(ctx, a, TCG_COND_EQ);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index a3997ed580..91f0ac32ff 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -4,6 +4,7 @@ dir = meson.current_source_dir()
gen = [
decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+ decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
]
riscv_ss = ss.source_set()
--
2.34.1
next prev parent reply other threads:[~2022-02-12 0:15 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-11 23:59 [PULL 00/40] riscv-to-apply queue Alistair Francis
2022-02-11 23:59 ` [PULL 01/40] include: hw: remove ibex_plic.h Alistair Francis
2022-02-11 23:59 ` [PULL 02/40] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-11 23:59 ` [PULL 03/40] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-11 23:59 ` [PULL 04/40] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-11 23:59 ` [PULL 05/40] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-11 23:59 ` [PULL 06/40] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 07/40] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-11 23:59 ` [PULL 08/40] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-12 0:00 ` Alistair Francis [this message]
2022-02-12 0:00 ` [PULL 10/40] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-12 0:00 ` [PULL 11/40] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-12 0:00 ` [PULL 12/40] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-12 0:00 ` [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 15/40] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-12 0:00 ` [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-12 0:00 ` [PULL 17/40] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-12 0:00 ` [PULL 18/40] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-12 0:00 ` [PULL 20/40] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-12 0:00 ` [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-12 0:00 ` [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-12 0:00 ` [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-12 0:00 ` [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-12 0:00 ` [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-02-12 0:00 ` [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-02-12 0:00 ` [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-02-12 0:00 ` [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-02-12 0:00 ` [PULL 33/40] docs/system: riscv: Document AIA options for " Alistair Francis
2022-02-12 0:00 ` [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-02-12 0:00 ` [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-12 0:00 ` [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-12 0:00 ` [PULL 37/40] target/riscv: add support for svnapot extension Alistair Francis
2022-02-12 0:00 ` [PULL 38/40] target/riscv: add support for svinval extension Alistair Francis
2022-02-12 0:00 ` [PULL 39/40] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-12 0:00 ` [PULL 40/40] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-15 11:39 ` [PULL 00/40] riscv-to-apply queue Peter Maydell
2022-02-16 6:28 ` Alistair Francis
2022-02-16 6:45 ` Anup Patel
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