From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
Anup Patel <anup@brainfault.org>, Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation
Date: Wed, 16 Feb 2022 16:28:53 +1000 [thread overview]
Message-ID: <20220216062912.319738-17-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com>
From: Anup Patel <anup.patel@wdc.com>
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-6-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 +++++
target/riscv/cpu.c | 11 +++--------
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f030cb58b2..283a3cda4b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -379,6 +379,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
return env->features & (1ULL << feature);
}
+static inline void riscv_set_feature(CPURISCVState *env, int feature)
+{
+ env->features |= (1ULL << feature);
+}
+
#include "cpu_user.h"
extern const char * const riscv_int_regnames[];
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f1c268415a..ff766acc21 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -135,11 +135,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
env->vext_ver = vext_ver;
}
-static void set_feature(CPURISCVState *env, int feature)
-{
- env->features |= (1ULL << feature);
-}
-
static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
@@ -508,18 +503,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
if (cpu->cfg.mmu) {
- set_feature(env, RISCV_FEATURE_MMU);
+ riscv_set_feature(env, RISCV_FEATURE_MMU);
}
if (cpu->cfg.pmp) {
- set_feature(env, RISCV_FEATURE_PMP);
+ riscv_set_feature(env, RISCV_FEATURE_PMP);
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
if (cpu->cfg.epmp) {
- set_feature(env, RISCV_FEATURE_EPMP);
+ riscv_set_feature(env, RISCV_FEATURE_EPMP);
}
}
--
2.34.1
next prev parent reply other threads:[~2022-02-16 8:35 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 6:28 [PULL v2 00/35] riscv-to-apply queue Alistair Francis
2022-02-16 6:28 ` [PULL v2 01/35] include: hw: remove ibex_plic.h Alistair Francis
2022-02-16 6:28 ` [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-16 6:28 ` [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-16 6:28 ` [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-16 6:28 ` [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-16 6:28 ` [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-16 6:28 ` [PULL v2 07/35] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-16 10:24 ` Philipp Tomsich
2022-02-16 22:14 ` Alistair Francis
2022-02-16 6:28 ` [PULL v2 08/35] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-16 6:28 ` [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-16 6:28 ` [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-16 6:28 ` [PULL v2 11/35] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-16 6:28 ` [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-16 6:28 ` [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-16 6:28 ` Alistair Francis [this message]
2022-02-16 6:28 ` [PULL v2 17/35] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-16 6:28 ` [PULL v2 18/35] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-16 6:28 ` [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-16 6:28 ` [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-16 6:28 ` [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-16 6:29 ` [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-16 6:29 ` [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-04-12 14:53 ` Peter Maydell
2022-04-13 23:59 ` Alistair Francis
2022-02-16 6:29 ` [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-16 6:29 ` [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-16 6:29 ` [PULL v2 32/35] target/riscv: add support for svnapot extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 33/35] target/riscv: add support for svinval extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 34/35] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 35/35] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-16 15:29 ` [PULL v2 00/35] riscv-to-apply queue Peter Maydell
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