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envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-id: 20220204174700.534953-12-anup@brainfault.org [ Changes by AF: - Fix possible unintilised variable error in rmw_sie() ] Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 128 ++++++++++++++++++++++++++++++++++++++++- target/riscv/machine.c | 2 + 3 files changed, 131 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dc2485bb4..f0e69f2871 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -209,6 +209,7 @@ struct CPURISCVState { uint64_t htimedelta; =20 /* Hypervisor controlled virtual interrupt priorities */ + target_ulong hvictl; uint8_t hviprio[64]; =20 /* Upper 64-bits of 128-bit CSRs */ @@ -512,6 +513,7 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *e= nv) return env->misa_mxl; } #endif +#define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) =20 #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d8283160b1..46448a2b7e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -234,6 +234,15 @@ static RISCVException pointer_masking(CPURISCVState = *env, int csrno) return RISCV_EXCP_ILLEGAL_INST; } =20 +static int aia_hmode(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static int aia_hmode32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -1142,6 +1151,9 @@ static RISCVException rmw_sie64(CPURISCVState *env,= int csrno, uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } ret =3D rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); } else { ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); @@ -1162,7 +1174,7 @@ static RISCVException rmw_sie(CPURISCVState *env, i= nt csrno, RISCVException ret; =20 ret =3D rmw_sie64(env, csrno, &rval, new_val, wr_mask); - if (ret_val) { + if (ret =3D=3D RISCV_EXCP_NONE && ret_val) { *ret_val =3D rval; } =20 @@ -1355,6 +1367,9 @@ static RISCVException rmw_sip64(CPURISCVState *env,= int csrno, uint64_t mask =3D env->mideleg & sip_writable_mask; =20 if (riscv_cpu_virt_enabled(env)) { + if (env->hvictl & HVICTL_VTI) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } ret =3D rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); } else { ret =3D rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); @@ -1741,6 +1756,110 @@ static RISCVException write_htimedeltah(CPURISCVS= tate *env, int csrno, return RISCV_EXCP_NONE; } =20 +static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->hvictl; + return RISCV_EXCP_NONE; +} + +static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) +{ + env->hvictl =3D val & HVICTL_VALID_MASK; + return RISCV_EXCP_NONE; +} + +static int read_hvipriox(CPURISCVState *env, int first_index, + uint8_t *iprio, target_ulong *val) +{ + int i, irq, rdzero, num_irqs =3D 4 * (riscv_cpu_mxl_bits(env) / 32); + + /* First index has to be a multiple of number of irqs per register *= / + if (first_index % num_irqs) { + return (riscv_cpu_virt_enabled(env)) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_IN= ST; + } + + /* Fill-up return value */ + *val =3D 0; + for (i =3D 0; i < num_irqs; i++) { + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero))= { + continue; + } + if (rdzero) { + continue; + } + *val |=3D ((target_ulong)iprio[irq]) << (i * 8); + } + + return RISCV_EXCP_NONE; +} + +static int write_hvipriox(CPURISCVState *env, int first_index, + uint8_t *iprio, target_ulong val) +{ + int i, irq, rdzero, num_irqs =3D 4 * (riscv_cpu_mxl_bits(env) / 32); + + /* First index has to be a multiple of number of irqs per register *= / + if (first_index % num_irqs) { + return (riscv_cpu_virt_enabled(env)) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_IN= ST; + } + + /* Fill-up priority arrary */ + for (i =3D 0; i < num_irqs; i++) { + if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero))= { + continue; + } + if (rdzero) { + iprio[irq] =3D 0; + } else { + iprio[irq] =3D (val >> (i * 8)) & 0xff; + } + } + + return RISCV_EXCP_NONE; +} + +static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + return read_hvipriox(env, 0, env->hviprio, val); +} + +static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong va= l) +{ + return write_hvipriox(env, 0, env->hviprio, val); +} + +static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *v= al) +{ + return read_hvipriox(env, 4, env->hviprio, val); +} + +static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong v= al) +{ + return write_hvipriox(env, 4, env->hviprio, val); +} + +static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *va= l) +{ + return read_hvipriox(env, 8, env->hviprio, val); +} + +static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong va= l) +{ + return write_hvipriox(env, 8, env->hviprio, val); +} + +static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *v= al) +{ + return read_hvipriox(env, 12, env->hviprio, val); +} + +static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong v= al) +{ + return write_hvipriox(env, 12, env->hviprio, val); +} + /* Virtual CSR Registers */ static RISCVException read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) @@ -2534,9 +2653,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, wr= ite_mtval2 }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, wr= ite_mtinst }, =20 + /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA= ) */ + [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write= _hvictl }, + [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, w= rite_hviprio1 }, + [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, w= rite_hviprio2 }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_= hidelegh }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_= hviph }, + [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, = write_hviprio1h }, + [CSR_HVIPRIO2H] =3D { "hviprio2h", aia_hmode32, read_hviprio2h, = write_hviprio2h }, [CSR_VSIEH] =3D { "vsieh", aia_hmode32, NULL, NULL, rmw_= vsieh }, [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_= vsiph }, =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 65e63031ba..dbd7bd0c83 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + + VMSTATE_UINTTL(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), =20 VMSTATE_UINT64(env.vsstatus, RISCVCPU), --=20 2.34.1