From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
Anup Patel <anup@brainfault.org>,
Alistair Francis <alistair.francis@wdc.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs
Date: Wed, 16 Feb 2022 16:29:00 +1000 [thread overview]
Message-ID: <20220216062912.319738-24-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com>
From: Anup Patel <anup.patel@wdc.com>
The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.
At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-13-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46448a2b7e..89700038fb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -158,6 +158,15 @@ static RISCVException any32(CPURISCVState *env, int csrno)
}
+static int aia_any(CPURISCVState *env, int csrno)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return any(env, csrno);
+}
+
static int aia_any32(CPURISCVState *env, int csrno)
{
if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -568,6 +577,12 @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException write_ignore(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2598,9 +2613,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
+ /* Virtual Interrupts for Supervisor Level (AIA) */
+ [CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
+ [CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
+
/* Machine-Level High-Half CSRs (AIA) */
[CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
[CSR_MIEH] = { "mieh", aia_any32, NULL, NULL, rmw_mieh },
+ [CSR_MVIENH] = { "mvienh", aia_any32, read_zero, write_ignore },
+ [CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
/* Supervisor Trap Setup */
@@ -2654,12 +2675,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+ [CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
[CSR_HVICTL] = { "hvictl", aia_hmode, read_hvictl, write_hvictl },
[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
+ [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL, rmw_hviph },
[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h },
[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h, write_hviprio2h },
--
2.34.1
next prev parent reply other threads:[~2022-02-16 6:55 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 6:28 [PULL v2 00/35] riscv-to-apply queue Alistair Francis
2022-02-16 6:28 ` [PULL v2 01/35] include: hw: remove ibex_plic.h Alistair Francis
2022-02-16 6:28 ` [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-16 6:28 ` [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-16 6:28 ` [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-16 6:28 ` [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-16 6:28 ` [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-16 6:28 ` [PULL v2 07/35] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-16 10:24 ` Philipp Tomsich
2022-02-16 22:14 ` Alistair Francis
2022-02-16 6:28 ` [PULL v2 08/35] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-16 6:28 ` [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-16 6:28 ` [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-16 6:28 ` [PULL v2 11/35] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-16 6:28 ` [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-16 6:28 ` [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-16 6:28 ` [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-16 6:28 ` [PULL v2 17/35] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-16 6:28 ` [PULL v2 18/35] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-16 6:28 ` [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-16 6:28 ` [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-16 6:28 ` [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-16 6:29 ` Alistair Francis [this message]
2022-02-16 6:29 ` [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-16 6:29 ` [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-16 6:29 ` [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-04-12 14:53 ` Peter Maydell
2022-04-13 23:59 ` Alistair Francis
2022-02-16 6:29 ` [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-16 6:29 ` [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-16 6:29 ` [PULL v2 32/35] target/riscv: add support for svnapot extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 33/35] target/riscv: add support for svinval extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 34/35] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 35/35] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-16 15:29 ` [PULL v2 00/35] riscv-to-apply queue Peter Maydell
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