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envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-id: 20220204174700.534953-14-anup@brainfault.org [ Changed by AF: - Fixup indentation ] Signed-off-by: Alistair Francis --- target/riscv/csr.c | 156 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 89700038fb..39402a6a49 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -194,6 +194,15 @@ static int smode32(CPURISCVState *env, int csrno) return smode(env, csrno); } =20 +static int aia_smode(CPURISCVState *env, int csrno) +{ + if (!riscv_feature(env, RISCV_FEATURE_AIA)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static int aia_smode32(CPURISCVState *env, int csrno) { if (!riscv_feature(env, RISCV_FEATURE_AIA)) { @@ -517,6 +526,8 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP= )) #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) =20 +#define VSTOPI_NUM_SRCS 5 + static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS; @@ -898,6 +909,28 @@ static RISCVException rmw_mieh(CPURISCVState *env, i= nt csrno, return ret; } =20 +static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) +{ + int irq; + uint8_t iprio; + + irq =3D riscv_cpu_mirq_pending(env); + if (irq <=3D 0 || irq > 63) { + *val =3D 0; + } else { + iprio =3D env->miprio[irq]; + if (!iprio) { + if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_M) { + iprio =3D IPRIO_MMAXIPRIO; + } + } + *val =3D (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; + *val |=3D iprio; + } + + return RISCV_EXCP_NONE; +} + static RISCVException read_mtvec(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1478,6 +1511,120 @@ static RISCVException write_satp(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static int read_vstopi(CPURISCVState *env, int csrno, target_ulong *val) +{ + int irq, ret; + target_ulong topei; + uint64_t vseip, vsgein; + uint32_t iid, iprio, hviid, hviprio, gein; + uint32_t s, scount =3D 0, siid[VSTOPI_NUM_SRCS], siprio[VSTOPI_NUM_S= RCS]; + + gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + hviid =3D get_field(env->hvictl, HVICTL_IID); + hviprio =3D get_field(env->hvictl, HVICTL_IPRIO); + + if (gein) { + vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + vseip =3D env->mie & (env->mip | vsgein) & MIP_VSEIP; + if (gein <=3D env->geilen && vseip) { + siid[scount] =3D IRQ_S_EXT; + siprio[scount] =3D IPRIO_MMAXIPRIO + 1; + if (env->aia_ireg_rmw_fn[PRV_S]) { + /* + * Call machine specific IMSIC register emulation for + * reading TOPEI. + */ + ret =3D env->aia_ireg_rmw_fn[PRV_S]( + env->aia_ireg_rmw_fn_arg[PRV_S], + AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, PRV_S, true, = gein, + riscv_cpu_mxl_bits(env)), + &topei, 0, 0); + if (!ret && topei) { + siprio[scount] =3D topei & IMSIC_TOPEI_IPRIO_MASK; + } + } + scount++; + } + } else { + if (hviid =3D=3D IRQ_S_EXT && hviprio) { + siid[scount] =3D IRQ_S_EXT; + siprio[scount] =3D hviprio; + scount++; + } + } + + if (env->hvictl & HVICTL_VTI) { + if (hviid !=3D IRQ_S_EXT) { + siid[scount] =3D hviid; + siprio[scount] =3D hviprio; + scount++; + } + } else { + irq =3D riscv_cpu_vsirq_pending(env); + if (irq !=3D IRQ_S_EXT && 0 < irq && irq <=3D 63) { + siid[scount] =3D irq; + siprio[scount] =3D env->hviprio[irq]; + scount++; + } + } + + iid =3D 0; + iprio =3D UINT_MAX; + for (s =3D 0; s < scount; s++) { + if (siprio[s] < iprio) { + iid =3D siid[s]; + iprio =3D siprio[s]; + } + } + + if (iid) { + if (env->hvictl & HVICTL_IPRIOM) { + if (iprio > IPRIO_MMAXIPRIO) { + iprio =3D IPRIO_MMAXIPRIO; + } + if (!iprio) { + if (riscv_cpu_default_priority(iid) > IPRIO_DEFAULT_S) { + iprio =3D IPRIO_MMAXIPRIO; + } + } + } else { + iprio =3D 1; + } + } else { + iprio =3D 0; + } + + *val =3D (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; + *val |=3D iprio; + return RISCV_EXCP_NONE; +} + +static int read_stopi(CPURISCVState *env, int csrno, target_ulong *val) +{ + int irq; + uint8_t iprio; + + if (riscv_cpu_virt_enabled(env)) { + return read_vstopi(env, CSR_VSTOPI, val); + } + + irq =3D riscv_cpu_sirq_pending(env); + if (irq <=3D 0 || irq > 63) { + *val =3D 0; + } else { + iprio =3D env->siprio[irq]; + if (!iprio) { + if (riscv_cpu_default_priority(irq) > IPRIO_DEFAULT_S) { + iprio =3D IPRIO_MMAXIPRIO; + } + } + *val =3D (irq & TOPI_IID_MASK) << TOPI_IID_SHIFT; + *val |=3D iprio; + } + + return RISCV_EXCP_NONE; +} + /* Hypervisor Extensions */ static RISCVException read_hstatus(CPURISCVState *env, int csrno, target_ulong *val) @@ -2613,6 +2760,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTVAL] =3D { "mtval", any, read_mtval, write_mtval = }, [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip = }, =20 + /* Machine-Level Interrupts (AIA) */ + [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, + /* Virtual Interrupts for Supervisor Level (AIA) */ [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, @@ -2642,6 +2792,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, =20 + /* Supervisor-Level Interrupts (AIA) */ + [CSR_STOPI] =3D { "stopi", aia_smode, read_stopi }, + /* Supervisor-Level High-Half CSRs (AIA) */ [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }= , [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }= , @@ -2680,6 +2833,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, w= rite_hviprio1 }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, w= rite_hviprio2 }, =20 + /* VS-Level Interrupts (H-extension with AIA) */ + [CSR_VSTOPI] =3D { "vstopi", aia_hmode, read_vstopi }, + /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_= hidelegh }, [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, write= _ignore }, --=20 2.34.1