From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
Anup Patel <anup@brainfault.org>,
Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs
Date: Wed, 16 Feb 2022 16:29:03 +1000 [thread overview]
Message-ID: <20220216062912.319738-27-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com>
From: Anup Patel <anup.patel@wdc.com>
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-16-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 203 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 203 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a186b31fcf..fe2c8dd40e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -942,6 +942,16 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
return CSR_VSISELECT;
case CSR_SIREG:
return CSR_VSIREG;
+ case CSR_SSETEIPNUM:
+ return CSR_VSSETEIPNUM;
+ case CSR_SCLREIPNUM:
+ return CSR_VSCLREIPNUM;
+ case CSR_SSETEIENUM:
+ return CSR_VSSETEIENUM;
+ case CSR_SCLREIENUM:
+ return CSR_VSCLREIENUM;
+ case CSR_STOPEI:
+ return CSR_VSTOPEI;
default:
return csrno;
};
@@ -1094,6 +1104,178 @@ done:
return RISCV_EXCP_NONE;
}
+static int rmw_xsetclreinum(CPURISCVState *env, int csrno, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ int ret = -EINVAL;
+ bool set, pend, virt;
+ target_ulong priv, isel, vgein, xlen, nval, wmask;
+
+ /* Translate CSR number for VS-mode */
+ csrno = aia_xlate_vs_csrno(env, csrno);
+
+ /* Decode register details from CSR number */
+ virt = set = pend = false;
+ switch (csrno) {
+ case CSR_MSETEIPNUM:
+ priv = PRV_M;
+ set = true;
+ pend = true;
+ break;
+ case CSR_MCLREIPNUM:
+ priv = PRV_M;
+ pend = true;
+ break;
+ case CSR_MSETEIENUM:
+ priv = PRV_M;
+ set = true;
+ break;
+ case CSR_MCLREIENUM:
+ priv = PRV_M;
+ break;
+ case CSR_SSETEIPNUM:
+ priv = PRV_S;
+ set = true;
+ pend = true;
+ break;
+ case CSR_SCLREIPNUM:
+ priv = PRV_S;
+ pend = true;
+ break;
+ case CSR_SSETEIENUM:
+ priv = PRV_S;
+ set = true;
+ break;
+ case CSR_SCLREIENUM:
+ priv = PRV_S;
+ break;
+ case CSR_VSSETEIPNUM:
+ priv = PRV_S;
+ virt = true;
+ set = true;
+ pend = true;
+ break;
+ case CSR_VSCLREIPNUM:
+ priv = PRV_S;
+ virt = true;
+ pend = true;
+ break;
+ case CSR_VSSETEIENUM:
+ priv = PRV_S;
+ virt = true;
+ set = true;
+ break;
+ case CSR_VSCLREIENUM:
+ priv = PRV_S;
+ virt = true;
+ break;
+ default:
+ goto done;
+ };
+
+ /* IMSIC CSRs only available when machine implements IMSIC. */
+ if (!env->aia_ireg_rmw_fn[priv]) {
+ goto done;
+ }
+
+ /* Find the selected guest interrupt file */
+ vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+ /* Selected guest interrupt file should be valid */
+ if (virt && (!vgein || env->geilen < vgein)) {
+ goto done;
+ }
+
+ /* Set/Clear CSRs always read zero */
+ if (val) {
+ *val = 0;
+ }
+
+ if (wr_mask) {
+ /* Get interrupt number */
+ new_val &= wr_mask;
+
+ /* Find target interrupt pending/enable register */
+ xlen = riscv_cpu_mxl_bits(env);
+ isel = (new_val / xlen);
+ isel *= (xlen / IMSIC_EIPx_BITS);
+ isel += (pend) ? ISELECT_IMSIC_EIP0 : ISELECT_IMSIC_EIE0;
+
+ /* Find the interrupt bit to be set/clear */
+ wmask = ((target_ulong)1) << (new_val % xlen);
+ nval = (set) ? wmask : 0;
+
+ /* Call machine specific IMSIC register emulation */
+ ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+ AIA_MAKE_IREG(isel, priv, virt,
+ vgein, xlen),
+ NULL, nval, wmask);
+ } else {
+ ret = 0;
+ }
+
+done:
+ if (ret) {
+ return (riscv_cpu_virt_enabled(env) && virt) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+ return RISCV_EXCP_NONE;
+}
+
+static int rmw_xtopei(CPURISCVState *env, int csrno, target_ulong *val,
+ target_ulong new_val, target_ulong wr_mask)
+{
+ bool virt;
+ int ret = -EINVAL;
+ target_ulong priv, vgein;
+
+ /* Translate CSR number for VS-mode */
+ csrno = aia_xlate_vs_csrno(env, csrno);
+
+ /* Decode register details from CSR number */
+ virt = false;
+ switch (csrno) {
+ case CSR_MTOPEI:
+ priv = PRV_M;
+ break;
+ case CSR_STOPEI:
+ priv = PRV_S;
+ break;
+ case CSR_VSTOPEI:
+ priv = PRV_S;
+ virt = true;
+ break;
+ default:
+ goto done;
+ };
+
+ /* IMSIC CSRs only available when machine implements IMSIC. */
+ if (!env->aia_ireg_rmw_fn[priv]) {
+ goto done;
+ }
+
+ /* Find the selected guest interrupt file */
+ vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
+
+ /* Selected guest interrupt file should be valid */
+ if (virt && (!vgein || env->geilen < vgein)) {
+ goto done;
+ }
+
+ /* Call machine specific IMSIC register emulation for TOPEI */
+ ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
+ AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI, priv, virt, vgein,
+ riscv_cpu_mxl_bits(env)),
+ val, new_val, wr_mask);
+
+done:
+ if (ret) {
+ return (riscv_cpu_virt_enabled(env) && virt) ?
+ RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -2930,6 +3112,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine-Level Interrupts (AIA) */
[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
+ /* Machine-Level IMSIC Interface (AIA) */
+ [CSR_MSETEIPNUM] = { "mseteipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MCLREIPNUM] = { "mclreipnum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MSETEIENUM] = { "mseteienum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MCLREIENUM] = { "mclreienum", aia_any, NULL, NULL, rmw_xsetclreinum },
+ [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei },
+
/* Virtual Interrupts for Supervisor Level (AIA) */
[CSR_MVIEN] = { "mvien", aia_any, read_zero, write_ignore },
[CSR_MVIP] = { "mvip", aia_any, read_zero, write_ignore },
@@ -2966,6 +3155,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Supervisor-Level Interrupts (AIA) */
[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
+ /* Supervisor-Level IMSIC Interface (AIA) */
+ [CSR_SSETEIPNUM] = { "sseteipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_SCLREIPNUM] = { "sclreipnum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_SSETEIENUM] = { "sseteienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_SCLREIENUM] = { "sclreienum", aia_smode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei },
+
/* Supervisor-Level High-Half CSRs (AIA) */
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
@@ -3013,6 +3209,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* VS-Level Interrupts (H-extension with AIA) */
[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
+ /* VS-Level IMSIC Interface (H-extension with AIA) */
+ [CSR_VSSETEIPNUM] = { "vsseteipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSCLREIPNUM] = { "vsclreipnum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSSETEIENUM] = { "vsseteienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSCLREIENUM] = { "vsclreienum", aia_hmode, NULL, NULL, rmw_xsetclreinum },
+ [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei },
+
/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
[CSR_HIDELEGH] = { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh },
[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero, write_ignore },
--
2.34.1
next prev parent reply other threads:[~2022-02-16 8:28 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 6:28 [PULL v2 00/35] riscv-to-apply queue Alistair Francis
2022-02-16 6:28 ` [PULL v2 01/35] include: hw: remove ibex_plic.h Alistair Francis
2022-02-16 6:28 ` [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-16 6:28 ` [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-16 6:28 ` [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-16 6:28 ` [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-16 6:28 ` [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-16 6:28 ` [PULL v2 07/35] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-16 10:24 ` Philipp Tomsich
2022-02-16 22:14 ` Alistair Francis
2022-02-16 6:28 ` [PULL v2 08/35] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-16 6:28 ` [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-16 6:28 ` [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-16 6:28 ` [PULL v2 11/35] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-16 6:28 ` [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-16 6:28 ` [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-16 6:28 ` [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-16 6:28 ` [PULL v2 17/35] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-16 6:28 ` [PULL v2 18/35] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-16 6:28 ` [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-16 6:28 ` [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-16 6:28 ` [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-16 6:29 ` Alistair Francis [this message]
2022-02-16 6:29 ` [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-16 6:29 ` [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-16 6:29 ` [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-04-12 14:53 ` Peter Maydell
2022-04-13 23:59 ` Alistair Francis
2022-02-16 6:29 ` [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-16 6:29 ` [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-16 6:29 ` [PULL v2 32/35] target/riscv: add support for svnapot extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 33/35] target/riscv: add support for svinval extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 34/35] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 35/35] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-16 15:29 ` [PULL v2 00/35] riscv-to-apply queue Peter Maydell
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