From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Yu Li <liyu.yukiteru@bytedance.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 35/35] docs/system: riscv: Update description of CPU
Date: Wed, 16 Feb 2022 16:29:12 +1000 [thread overview]
Message-ID: <20220216062912.319738-36-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220216062912.319738-1-alistair.francis@opensource.wdc.com>
From: Yu Li <liyu.yukiteru@bytedance.com>
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index fa016584bf..08ce3c4177 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -23,9 +23,9 @@ The ``virt`` machine supports the following devices:
* 1 generic PCIe host bridge
* The fw_cfg device that allows a guest to obtain data from QEMU
-Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
-can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
-enables the hypervisor extension for RV64.
+The hypervisor extension has been enabled for the default CPU, so virtual
+machines with hypervisor extension can simply be used without explicitly
+declaring.
Hardware configuration information
----------------------------------
--
2.34.1
next prev parent reply other threads:[~2022-02-16 9:03 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 6:28 [PULL v2 00/35] riscv-to-apply queue Alistair Francis
2022-02-16 6:28 ` [PULL v2 01/35] include: hw: remove ibex_plic.h Alistair Francis
2022-02-16 6:28 ` [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-16 6:28 ` [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-16 6:28 ` [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-16 6:28 ` [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-16 6:28 ` [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-16 6:28 ` [PULL v2 07/35] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-16 10:24 ` Philipp Tomsich
2022-02-16 22:14 ` Alistair Francis
2022-02-16 6:28 ` [PULL v2 08/35] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-16 6:28 ` [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-16 6:28 ` [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-16 6:28 ` [PULL v2 11/35] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-16 6:28 ` [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-16 6:28 ` [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-16 6:28 ` [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-16 6:28 ` [PULL v2 17/35] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-16 6:28 ` [PULL v2 18/35] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-16 6:28 ` [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-16 6:28 ` [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-16 6:28 ` [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-16 6:29 ` [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-16 6:29 ` [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-04-12 14:53 ` Peter Maydell
2022-04-13 23:59 ` Alistair Francis
2022-02-16 6:29 ` [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-16 6:29 ` [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-16 6:29 ` [PULL v2 32/35] target/riscv: add support for svnapot extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 33/35] target/riscv: add support for svinval extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 34/35] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-16 6:29 ` Alistair Francis [this message]
2022-02-16 15:29 ` [PULL v2 00/35] riscv-to-apply queue Peter Maydell
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