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envelope-from=prvs=039576d22=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philipp Tomsich The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow copies (in DisasContext) of some of the elements available in the RISCVCPUConfig structure. This commit redirects accesses to use the cfg_ptr copied into DisasContext and removes the shallow copies. Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Message-Id: <20220202005249.3566542-4-philipp.tomsich@vrull.eu> [ Changes by AF: - Fixup checkpatch failures ] Signed-off-by: Alistair Francis --- target/riscv/translate.c | 14 --- target/riscv/insn_trans/trans_rvi.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 146 ++++++++++++++-------- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- 4 files changed, 97 insertions(+), 69 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 49e40735ce..f19d5cd0c0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -77,11 +77,6 @@ typedef struct DisasContext { RISCVMXL ol; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool ext_ifencei; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zve32f; - bool ext_zve64f; bool hlsx; /* vector extension */ bool vill; @@ -99,8 +94,6 @@ typedef struct DisasContext { */ int8_t lmul; uint8_t sew; - uint16_t vlen; - uint16_t elen; target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; @@ -910,13 +903,6 @@ static void riscv_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); - ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; - ctx->ext_zfh =3D cpu->cfg.ext_zfh; - ctx->ext_zfhmin =3D cpu->cfg.ext_zfhmin; - ctx->ext_zve32f =3D cpu->cfg.ext_zve32f; - ctx->ext_zve64f =3D cpu->cfg.ext_zve64f; - ctx->vlen =3D cpu->cfg.vlen; - ctx->elen =3D cpu->cfg.elen; ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS)= ; ctx->mstatus_hs_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS)= ; ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_= trans/trans_rvi.c.inc index 3cd1b3f877..f1342f30f8 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -806,7 +806,7 @@ static bool trans_fence(DisasContext *ctx, arg_fence = *a) =20 static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) { - if (!ctx->ext_ifencei) { + if (!ctx->cfg_ptr->ext_ifencei) { return false; } =20 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_= trans/trans_rvv.c.inc index f85a9e83b4..275fded6e4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -74,7 +74,7 @@ static bool require_zve32f(DisasContext *s) } =20 /* Zve32f doesn't support FP64. (Section 18.2) */ - return s->ext_zve32f ? s->sew <=3D MO_32 : true; + return s->cfg_ptr->ext_zve32f ? s->sew <=3D MO_32 : true; } =20 static bool require_scale_zve32f(DisasContext *s) @@ -85,7 +85,7 @@ static bool require_scale_zve32f(DisasContext *s) } =20 /* Zve32f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <=3D MO_16 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <=3D MO_16 : true; } =20 static bool require_zve64f(DisasContext *s) @@ -96,7 +96,7 @@ static bool require_zve64f(DisasContext *s) } =20 /* Zve64f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <=3D MO_32 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <=3D MO_32 : true; } =20 static bool require_scale_zve64f(DisasContext *s) @@ -107,7 +107,7 @@ static bool require_scale_zve64f(DisasContext *s) } =20 /* Zve64f doesn't support FP64. (Section 18.2) */ - return s->ext_zve64f ? s->sew <=3D MO_16 : true; + return s->cfg_ptr->ext_zve64f ? s->sew <=3D MO_16 : true; } =20 /* Destination vector register group cannot overlap source mask register= . */ @@ -174,7 +174,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs= 1, TCGv s2) TCGv s1, dst; =20 if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || + s->cfg_ptr->ext_zve64f)) { return false; } =20 @@ -210,7 +211,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv= s1, TCGv s2) TCGv dst; =20 if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f || + s->cfg_ptr->ext_zve64f)) { return false; } =20 @@ -248,7 +250,7 @@ static bool trans_vsetivli(DisasContext *s, arg_vseti= vli *a) /* vector register offset from env */ static uint32_t vreg_ofs(DisasContext *s, int reg) { - return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8; + return offsetof(CPURISCVState, vreg) + reg * s->cfg_ptr->vlen / 8; } =20 /* check functions */ @@ -318,7 +320,8 @@ static bool vext_check_st_index(DisasContext *s, int = vd, int vs2, int nf, * when XLEN=3D32. (Section 18.2) */ if (get_xl(s) =3D=3D MXL_RV32) { - ret &=3D (!has_ext(s, RVV) && s->ext_zve64f ? eew !=3D MO_64 : t= rue); + ret &=3D (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? eew !=3D MO_64 : true); } =20 return ret; @@ -454,7 +457,7 @@ static bool vext_wide_check_common(DisasContext *s, i= nt vd, int vm) { return (s->lmul <=3D 2) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->elen >> 4)) && + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)) && require_align(vd, s->lmul + 1) && require_vm(vm, vd); } @@ -482,7 +485,7 @@ static bool vext_narrow_check_common(DisasContext *s,= int vd, int vs2, { return (s->lmul <=3D 2) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->elen >> 4)) && + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)) && require_align(vs2, s->lmul + 1) && require_align(vd, s->lmul) && require_vm(vm, vd); @@ -661,7 +664,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, = uint32_t data, * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. */ - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -819,7 +823,8 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t r= s1, uint32_t rs2, mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); stride =3D get_gpr(s, rs2, EXT_NONE); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -925,7 +930,8 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs= 1, uint32_t vs2, mask =3D tcg_temp_new_ptr(); index =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); @@ -1065,7 +1071,8 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, u= int32_t data, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); base =3D get_gpr(s, rs1, EXT_NONE); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -1120,7 +1127,8 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t = rs1, uint32_t nf, =20 uint32_t data =3D FIELD_DP32(0, VDATA, NF, nf); dest =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 base =3D get_gpr(s, rs1, EXT_NONE); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); @@ -1185,7 +1193,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) static inline uint32_t MAXSZ(DisasContext *s) { int scale =3D s->lmul - 3; - return scale < 0 ? s->vlen >> -scale : s->vlen << scale; + return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << = scale; } =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) @@ -1220,7 +1228,8 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen= 3Fn *gvec_fn, data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); } mark_vs_dirty(s); gen_set_label(over); @@ -1262,7 +1271,8 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, = uint32_t vs2, uint32_t vm, =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1425,7 +1435,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, = uint32_t vs2, uint32_t vm, =20 data =3D FIELD_DP32(data, VDATA, VM, vm); data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -1508,7 +1519,8 @@ static bool do_opivv_widen(DisasContext *s, arg_rmr= r *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); @@ -1587,7 +1599,8 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmr= r *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); return true; @@ -1663,7 +1676,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -1843,7 +1857,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -1963,7 +1978,8 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmr= r *a) * are not included for EEW=3D64 in Zve64*. (Section 18.2) */ return opivv_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true= ); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a) @@ -1976,7 +1992,8 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmr= r *a) * are not included for EEW=3D64 in Zve64*. (Section 18.2) */ return opivx_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true= ); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) @@ -2046,7 +2063,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_= v_v *a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - cpu_env, s->vlen / 8, s->vlen / 8, data, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); gen_set_label(over); } @@ -2083,7 +2101,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_= v_x *a) }; =20 tcg_gen_ext_tl_i64(s1_i64, s1); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8= , data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data= )); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1_i64, cpu_env, desc); =20 @@ -2123,7 +2142,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_= v_i *a) =20 s1 =3D tcg_constant_i64(simm); dest =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8= , data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data= )); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, cpu_env, desc); =20 @@ -2176,7 +2196,8 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmr= r *a) * for EEW=3D64 in Zve64*. (Section 18.2) */ return opivv_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true= ); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a) @@ -2187,7 +2208,8 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmr= r *a) * for EEW=3D64 in Zve64*. (Section 18.2) */ return opivx_check(s, a) && - (!has_ext(s, RVV) && s->ext_zve64f ? s->sew !=3D MO_64 : true= ); + (!has_ext(s, RVV) && + s->cfg_ptr->ext_zve64f ? s->sew !=3D MO_64 : true); } =20 GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check) @@ -2275,7 +2297,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2302,7 +2325,8 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, = uint32_t vs2, dest =3D tcg_temp_new_ptr(); mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data))= ; + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); @@ -2391,7 +2415,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2464,7 +2489,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr = *a) \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2583,7 +2609,8 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fn); + s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); return true; @@ -2696,7 +2723,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfm= v_v_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); =20 dest =3D tcg_temp_new_ptr(); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8= , data)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data= )); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); =20 fns[s->sew - 1](dest, t1, cpu_env, desc); @@ -2782,7 +2810,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2831,7 +2860,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2896,7 +2926,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2947,7 +2978,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -2986,7 +3018,7 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_check(s, a) && (s->sew < MO_64) && - ((s->sew + 1) <=3D (s->elen >> 4)); + ((s->sew + 1) <=3D (s->cfg_ptr->elen >> 4)); } =20 GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) @@ -3034,7 +3066,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a)= \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, fn); \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, fn); \ mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ @@ -3067,7 +3100,8 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr = *a) mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); dst =3D dest_gpr(s, a->rd); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, da= ta)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -3099,7 +3133,8 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr= *a) mask =3D tcg_temp_new_ptr(); src2 =3D tcg_temp_new_ptr(); dst =3D dest_gpr(s, a->rd); - desc =3D tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, da= ta)); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data)); =20 tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); @@ -3134,7 +3169,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *= a) \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ - cpu_env, s->vlen / 8, s->vlen / 8, \ + cpu_env, s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, \ data, fn); \ mark_vs_dirty(s); \ gen_set_label(over); \ @@ -3174,7 +3210,8 @@ static bool trans_viota_m(DisasContext *s, arg_viot= a_m *a) }; tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); return true; @@ -3200,7 +3237,8 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v = *a) gen_helper_vid_v_w, gen_helper_vid_v_d, }; tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - cpu_env, s->vlen / 8, s->vlen / 8, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); @@ -3554,7 +3592,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_= rmrr *a) =20 if (a->vm && s->vl_eq_vlmax) { int scale =3D s->lmul - (s->sew + 3); - int vlmax =3D scale < 0 ? s->vlen >> -scale : s->vlen << scale; + int vlmax =3D scale < 0 ? + s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << = scale; TCGv_i64 dest =3D tcg_temp_new_i64(); =20 if (a->rs1 =3D=3D 0) { @@ -3586,7 +3625,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_= rmrr *a) =20 if (a->vm && s->vl_eq_vlmax) { int scale =3D s->lmul - (s->sew + 3); - int vlmax =3D scale < 0 ? s->vlen >> -scale : s->vlen << scale; + int vlmax =3D scale < 0 ? + s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << = scale; if (a->rs1 >=3D vlmax) { tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); @@ -3638,7 +3678,8 @@ static bool trans_vcompress_vm(DisasContext *s, arg= _r *a) data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->vlen / 8, s->vlen / 8, data, + cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); gen_set_label(over); @@ -3657,7 +3698,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAM= E * a) \ if (require_rvv(s) && = \ QEMU_IS_ALIGNED(a->rd, LEN) && = \ QEMU_IS_ALIGNED(a->rs2, LEN)) { = \ - uint32_t maxsz =3D (s->vlen >> 3) * LEN; = \ + uint32_t maxsz =3D (s->cfg_ptr->vlen >> 3) * LEN; = \ if (s->vstart =3D=3D 0) { = \ /* EEW =3D 8 */ = \ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), = \ @@ -3742,7 +3783,8 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a,= uint8_t seq) =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, - s->vlen / 8, s->vlen / 8, data, fn); + s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); =20 mark_vs_dirty(s); gen_set_label(over); diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/ins= n_trans/trans_rvzfh.c.inc index 5a7cac8958..608c51da2c 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -17,13 +17,13 @@ */ =20 #define REQUIRE_ZFH(ctx) do { \ - if (!ctx->ext_zfh) { \ + if (!ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ - if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \ + if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ } while (0) --=20 2.34.1